I just assembled the newest batch of PCBs based on my latest changes to the design. My goal is to condense some of the component boards together to save a bit of room on the backplane, either to allow a smaller backplane or just to leave more room for experiments.
Three boards were in the most need of an update: the CPU, the memory, and the clock/decoder boards.
My CPU board previously contained the 65C02 CPU and not much else. I experimented with some different configurations of the PHI2 and PHI2O clock signals, but settled on just using the oscillator clock across the whole system and ignoring the PHI2O output signal from the 65C02 entirely. I think this also in the design recommendations for the latest WDC chips anyway - should have listened.
Since there was so much room on the CPU board, I moved the GAL and clock oscillator on there as well. The only reason for these being separated originally was to allow an FPGA to do the address decoding and glue logic, but I'm happy with the performance (and price) of the ATF16V8B GAL for this purpose.
The new memory board is really just a doubled-up version of the existing memory board. It has two slots for DIP-28 RAM or ROM chips with jumpers to configure each one individually. The two chips can be any combination of 8KB or 32KB ROM or RAM and multiple boards can installed simultaneously. The chip enable for each chip is driven by the onboard jumpers and the address decoder lines so memory layout is pretty flexible. For now, though, I will stick with the 8KB ROM and 32KB RAM on one board as this is enough for all the code I've been running. One note: there is no memory banking, so there's still a limit of 64KB total memory (including I/O space). I think I've decided bank switching is out of scope for this project anyway.
These boards are getting pretty close to what I'd consider the final design for Herring. I have a few more small tweaks to the system bus layout. There is another round of PCBs in the mail already to address these final issues and, more importantly, make them all the same color.
In the meantime, I'm cleaning up the schematics and documentation with plans to release everything after a final review.