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• Final Prototype and Reflections

  Dave Collins • 11/09/2021 at 16:34 • 0 comments

  Introduction
  

  It's interesting how these projects can take a completely different direction than when you started out.  About 2 weeks ago I decided that this project had kind of a turn off the road, and the reason that happened is, in my mission to make the project as absurd as I possibly could I'd really set some design goals that should not have existed.  I set out to see if I could make a CPU from op amps. If you know me,  then you know when I set goals like that unless something else pops my interest  I'll probably build a CPU from op amps... the only trouble was I'd greatly underestimated the size of that rabbit hole. 
  

  Building a digital CPU from what is essentially an analog competitor has consistently more variables and pit falls than traditional logic.   Don't get me wrong, I work in telecom, I spend 8-13 hours a day looking at spectrum readings on a scope I am well aware of the analog component to digital signaling, I knew this would be difficult on the outset.  What I did not understand going into this would be the time sink that this type of project would create... and for a while that was great I was definitely not bored, after all I like solving problems from data and signal readings I am a annalist.
  
  Also, as I continued to prototype and build this thing up on the bread board it became clear that, though it would absolutely be possible to build a 1-bit CPU from op amps on a bread board; it was basically just a large state machine.  Additionally,  the more and more I built, the more I started to realize that at the end of this I was really excited for the state machine build.  And with that excitement came the realization that I was simply delaying the project that I wanted to do in order to optimize the project that I was really just interested in for it's absurdity.
  

  
  

  OPEN LOOP?
  I get this question a lot.  the answer is yes, when the op amp is in open loop its basically a really inefficient comparator.  essentially when the voltage on the input side of the gate's input pin is less than the voltage at the divider on the opposed input pin the gate is in cut off, and when it is greater than the voltage at the divider it "rails out and registers a high signal (close to but not exactly the same as the VCC of the circuit.  Also important to note the source voltage pins are tied to +12v and GND at the positive and negative input pins respectively. The High state on an open loop op amp is generally "good enough" to trigger another gate in a combinational logic setup.

  The ALU Design
  

  The turning point for me was running into Ken Shirriff's blog on the Z-80 ALU.  Its an interesting read if you have the time (and its short so I highly recommend it!).  He goes in to great detail the design of the Z-80 4-bit ALU.  You heard that right, 4 bits ALU for a 8 bit CPU.  He also lays out a very good explanation of the inner workings for the 1-bit calculation cell used on the chip for the 4-bit alu.   It was so fun to read I thought i'd build it up in Logism:
  
  

  
  As you can see as simple as it gets; it has an 8 bit multiplexer built in ... and is so simple it relies on further logic to drive the inputs for 2 component comparison (it only has 3 way gates, and certain states must be asserted by the rest of the CPU to produce proper calculations).  In fact, as I read, I became hooked on this design and thought it would be no problem to build it up on a bread board with op amps.

  It probably took about another week to build this in afternoons after work, and then another two days to troubleshoot values to really get it working.   But in the end I did end up with a fully functioning ALU:
  

  
  

  It's an interesting little thing to play with; I'll be honest some times i just plug it in and push the buttons just to appreciate the absurdity of what is really going on here.  But honestly...

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• Logism Diagram

  Dave Collins • 10/19/2021 at 18:45 • 0 comments

  The ALU is mostly completed; I have built the proof of concept so now is on to building the ALU and it's 4 bit decode (actually 3). I was able to omit an additional XOR GATE (a savings of 1 whole package!). This was done by taking the results of the first XOR gate from the full adder.  I'll be the first to admit Its not the best design but I was shooting for as few gates as possible to try to keep the package count under 4.  I made a major decision that I'll be using diodes to make some of the OR gates; as it's going to be VERY complex otherwise.    The 3 bit command word selects between ADD WITH CARRY, SUBTRACT WITH BORROW, AND, OR, XOR, NAND, NOR, AND XNOR.  I opted for leaving in NOR and OR, as they can be used in place of LOAD 1 or LOAD 0 as the result is predictable based on the data bus.   This allows me to omit this instruction in the command register for memory operations.  The remaining 4th bit puts the whole ALU circuit into cut off, this is convenient because the memory and bus control register will also have a 3 bit command word; though the forth bit will be used to cut off the control register in a low state (as opposed to a high state cutting off the ALU).  I will more than likely microcode this using an eeprom but for now next will be the D flip flops for the Results register, and the CB Flag.
  

• Proof of concept completed

  Dave Collins • 09/22/2021 at 03:15 • 0 comments

  I completed an initial proof of concept; which is a simple ALU.  The current proof of concept has 1 bug which is the carry / borrow big resolves; even if the MU (math unit) is not selected. This is due to the proof of concept resolving all of the functions and only outputting the selected function.   The next logical step is to create a control register which will allow only 1 function to output.   The ALU currently supports the following functions add with carry, subtract with borrow, AND, OR, and XOR (and their inverse values).
  

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