Homemade Successive Approximation Register ADC

This is a homemade 7-bit SAR ADC using discrete components for principle study.

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The following is an introduction to a Successive Approximation Register Analog to Digital Converter (SAR ADC) that I made myself for principle study, and observing the conversion behavior inside the SAR ADC allows you to experience the operation of both analog and digital circuits. In 1979, I made my own 8-bit digital sampling unit for analog oscilloscopes of attached files photos (IMAGE_055 & IMAGE_043), and this is a recent reproduction of that SAR ADC in 7-bit format. The concepts are as follows.

(1) The SAR will consist of as few as general standard logic ICs.
(2) A self-running mode will be provided so that the behavior of the ADC can be observed with this board alone.

The detail chapter shows the schematic of this SAR ADC and the video shows how the DA conversion signal of the SAR output converges to the input voltage.

1. Circuit of the SAR ADC

    Figure 1 shows the SAR ADC board and Fig. 2 is the schematic.

                                                    Fig. 1 Circuit board of the SAR ADC

                                                              Fig. 2 Schematic of the SAR ADC

    The IC1 is an 8-bit shift register. The IC2, 3, 4, and 5 are D-FFs to hold the comparison result of the comparator IC11. The IC6 and IC7 are gates that take the logical product of the shift register output and the D-FF output. The IC9 is a register for holding the AD conversion result. The D1 to D7 are LEDs for displaying the binary data of conversion results. The clock to operate the SAR is generated by an astable multivibrator configured with IC8. The clock period is 103 us and the conversion time is 824 us. The dynamic range of the input signal is from 0 V to 5 V and the output bit width is 7-bit. 0 V is converted to binary '0000000' and 5 V to '1111111'.

2. Internal DAC

    The internal Digital to Analog Converter (DAC) that generates the comparison signal with the input signal was configured with R-2R resistor ladder. Normally, it is preferable to use fixed register ladder networks, which have high accuracy, but here, for training purposes, I used individual resistors. The dispersion of the resistors is 1% in actual measurement.

3. Sample-and-Hold

    If the input signal changes during conversion, the conversion result will be incorrect, so the ADC needs a sample-and-hold. The sample-and-hold can be composed of an op amp and a FET switch, but here I used a monolithic IC, LF398 [2]. Fig. 3 shows an example of a sine waveform input signal and sample-and-hold output signal displayed on an oscilloscope.

                                                         Fig. 3 Sine input signal and sample-and-hold signal.

4. Operation of the SAR

    Figure 4 shows the SAR timing. The lowercase symbols in the figure correspond to the symbols of the signals in the schematic in Fig. 2. 

                                                                  Fig.4 Timing diagram of the SAR ADC

    As shown in ‘a’ to ‘d’ of Fig. 4, the shift register of IC1 supplies the rising edge signals, which is shifted by one clock, to the trigger input of D-FFs. This trigger signal causes the D-FF to hold the judgment result of the comparator, as shown in ‘g ‘to ‘n’ in Fig. 4.

    In the first step 0 of the SAR operation, all the output bits of the shift register IC1 are cleared to zero, and the output bits of the D-FFs of IC2 to IC5 are all preset to '1'. Each time it move to the next step, the next bit of the shift register is set to ‘1’, and the output of the DAC is add or subtract with a weighting by half of previous, and a judgment is made as to whether it is large or small in relation to the input signal.

    The following example shows a case where the input signal is 1.74V. At the beginning of the conversion operation of the step 0, a 2.5V signal, which is half of the dynamic range ('1000000'), is output from the DAC and compared with the input signal by the comparator. Since the comparison signal is larger than the input signal in the step 0, the comparator output 'r' becomes '0'. Then the D-FF output 'g' becomes '0' in the next step 1.


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8-bit digital sampling unit for analog oscilloscopes in 1979.

JPEG Image - 200.61 kB - 10/18/2021 at 01:12



Inside of 8-bit digital sampling unit for analog oscilloscopes in 1979.

JPEG Image - 233.01 kB - 10/18/2021 at 01:10



PDF version schematic.

Adobe Portable Document Format - 77.15 kB - 09/23/2021 at 12:15



Test program to control the SAR ADC by the computer PERSEUS-8 and interpreter CI-2.

Adobe Portable Document Format - 19.05 kB - 09/23/2021 at 12:10


  • 1 × SN74HC04 Logic ICs / Buffers, Drivers, Transceivers
  • 2 × SN74HC08 Logic ICs / Gates and Inverters
  • 4 × SN74HC74 Logic ICs / Flip-Flops, Latches, Registers
  • 2 × SN74HC273 Logic ICs / Flip-Flops, Latches, Registers
  • 1 × LF398 Amplifier and Linear ICs / Sample and Hold Amplifiers

View all 6 components

  • SAR ADC project log

    Mitsuru Yamada3 hours ago 0 comments

    1. The article was first posted on Sep. 23, 2021

    2. Revised on Oct. 18, 2021

          Added photos IMAGE_055 and IMAGE_043 of my own 8-bit digital sampling unit for analog oscilloscopes in 1979. 

View project log

Enjoy this project?



Mike Szczys wrote 5 days ago point

Thank you so much for sharing this project. I've grown up with ADCs inside every microcontroller and haven't taken the time to understand what one built from discrete hardware would look like. Your demonstration makes it easy to see what is happening and I had fun time learning about the circuit!

  Are you sure? yes | no

Mitsuru Yamada wrote 4 days ago point

You are welcome. I will never forget the excitement I felt when I observed the behavior of this self-made circuit with an oscilloscope when I was young. I felt that I had grasped for myself an important truth that relates both the analog and digital worlds.

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lamikam wrote 10/08/2021 at 19:09 point

Love it!

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Mitsuru Yamada wrote 10/08/2021 at 23:03 point

Thanks! As you can see in the gallery photos and attached file source, I was also able to control it with my own interpreter on my own computer. The value on the right side of the execution example below the source program is the voltage value converted from the reading.

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vegetableswim wrote 09/24/2021 at 04:02 point

So cool! Remind me of the discrete 555

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Mitsuru Yamada wrote 09/24/2021 at 05:54 point

Thanks. The 555 is an excellent IC. Actually, I was thinking of using a 555 monolithic IC for clock oscillation in this circuit at first. In the end, I made a astable multivibrator with a leftover part of the 74HC04 inverter, but it is not good stable.

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don.ware wrote 09/23/2021 at 14:05 point

As always, this is an excellent presentation from you. I will have to sit quietly and study it further....

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Mitsuru Yamada wrote 09/24/2021 at 00:17 point

Thanks, there are a lot of articles on the net explaining the SAR DAC, but there don't seem to be many that also show it in action on a handmade circuit, so I posted this one.

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