The new revision on Github has a few differences to the last tested version. 

On r0 pin 15 of U20 (Chip enable of the VGA signal) is connected to ground. On r1 it is connected to the inverted reset signal(through a spare inverter on U14) through a pullup resistor. 

Technically this should make it possible to RC-delay the VGA output signal until the VRAM is cleared by code - instead of having random data in the blanking periods that could damage a real CRT screen. 

If this was really ~1979 I would definitely implement the VGA blanking periods in hardware.