U8 ("ZPAL") - the glue logic for the onboard Z80 microcomputer
The Z80’s memory map is as follows
0000H-5FFF H:ROM 6000H-7FFF Common RAM bank H: 8000H-FFFF Switching RAM bank H:
So that the Z80 may access all of the possible 64 kbytes of RAM whilst still reading from the ROM, the RAM is split into two 32k halves.
Only one of these halves may appear in the top 32k of address space at a time. When the ‘BANK’ signal is low the data in RAM0 (IC1) is accessible in this address range; when ‘BANK’ is high the data in RAM1 (IC2) is accessible.
If 8 kbyte RAM chips are loaded in the board then only the first 8 kbytes of this 32k address space are useful. The first 8 kbytes of RAM is always accessible in the common bank. The ‘MAP’ signal is not used at present.
The Z80’s I/O port address map is as follows:
Address Name Function 00H PORT Read only input port. 08H LATCH Read/write disk select latch 10H ZINTS Write: interrupt the 1616. 10H ZCLRINT Read: clear pending Z80 interrupt. 18H SDATA Read/write 1616 communications port. 20H SCSIBASE SCSI controller base address 40H FDCBASE Floppy disk controller base address. 60H SCCBASE Serial communications controller base address.
The input port enables a Z80 program to determine the level of the following signals:
Bit 0: The ‘SCOMMAND’ signal is set when the byte from the 1616 which is currently held in the receive latch is a command, meaning that the MC68000 put the data there by writing to its ‘SCOMMAND’ output port.
Bit 1: The ‘ZRXRDY’ signal is high if there is a data or command byte from the MC68000 within the receive register.
Bit 2: The ‘ZTXRDY’ signal is high if the 1616 has read the previous byte out of the transmit register.
Bit 3: This signal determines whether the Z80 is to enter its normal operating mode or to execute its diagnostic test mode.
Again, does not look difficult.