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Logic strips

Attempting to lower the cost and augment flexibility of discrete logic designs.

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I'm just scratching an itch here but "you never know" so here is a dedicated page because the comments thread got quite excessive on the TTLers project page.

As the name implies, it's a strip of PCB with logic functions soldered on it.
A bit like a LED strip but not flexible and, instead of emitting light, it's like a cut-to-measure strip to provide basic, identical functions.
Like a dumb SIP package, but you decide how long it is.
It can implement any basic logic function but usually it's NOR (or whatever you decide).
It can use "littlegates", RTL, DCTL, DTL, LEDTL, ECL, TTL, CMOS, IIL, in germanium or silicon, as you like.
It is easy to manufacture en mass at low cost to speed up your discrete logic projects.
And it is meant to be used by Tim's VHDL-to-discrete-logic flow.

This project is a logical (hmmm) consequence of Tim's project #VHDL/Verilog to Discrete Logic Flow as discussed in the comments of the #TTLers project page.

The whole point of this project is to reduce the cost and pain of soldering hundreds, thousands of identical parts, either through-hole or SMD, when building a reasonably elaborate project. When you reach the scale of a small processor, such as Tim's MCPU seen below, automated pick-and-place and batch soldering are not an option anymore.

Now, automation is Tim's central idea. But wait, don't we have integrated circuits these days ? Of course we do but they come in fixed sizes, traditionally in DIP packages.

Creating and producing cheap strips of logic gates makes it more convenient and cost-effective for prototypes for example. Identical gates can be cheaply built by machines and then cut-to-measure when and where needed. The designer can then focus more closely on the main board and its routing, as only the connections with the strips need to be soldered (like traditional DIP TTL chips).

But the strips can implement whatever logic family one desires, thus separating architecture from low-level technology. Or so I hope because each family has their own "best flavour" (mostly NOR).

Now I hear you thinking: "yg has another brainfart and nothing tangible to show", as it happens so often. So I already took a few hours (I didn't time it) to make a first "early rendering" based on the gate I already tested for 2ns propagation delay. First let's look at the updated schematic:

I have followed Tim's method of putting one identical pull-up resistor at the input of the inverter, instead of the output, where the fanout rules dictate an adapted resistor value for each gate. Otherwise it's pretty much what I had tested in the RO9 circuit.

There is only one input because the gates work in "open collector" unlike more modern gates (after all it's 1966 technology, what did you expect?)

Using SMD parts only, the gate can be quite compact.

  • A full reel of MMBT2369 will cost you about 150$ these days, or around $0.05 per part. How far have we gone in 50 years !
  • The resistors and capacitors are 0603, nothing special about it. I could have gone to 0201 because I have the option in EAGLE but it will depend on the factory's stocks.
  • The diode is a Schottky type in SOD323, rated at < 2pF. The RBV751 is NRND but you could find appropriate equivalent parts.

Routing it all on dual-sided PCB was not difficult. It's a first try so don't take it too seriously but it's an interesting approximate.

One side has only passives, the other has the actives. Cheap factories might not provide dual-sided oven soldering so the probable method is to ask to solder only the cheap tiny passives, since the transistors and diodes might come from personal stock and sending it to China might be cumbersome.

One side provides the positive supply rail, the other has a reference/ground. A ground pin increase signal integrity for the nets that are perpendicular to the strip direction.

It could be more compact but it's only a first try...

In the above case, about 8 lines of 13 "gates" fit in 100mm×100mm, or 104 gates on the standard DirtyPCB offer. That would bring you about 1040 bare PCB gates for about 17USD.

Concerning the solder : the PCB could be milled to cut the pads in the middle to allow direct soldering, without connector or pin or...

Apart from perpendicular grounding nets, the "motherboard" mainly deals with signal distribution so the router has an easier task. The strips provide ample current and decoupling, which relieves the motherboard.

Now, we need "strips" with different technologies : NMOS, Light Logic, CMOS, I²L, LTL, ECL, TTL, germanium, ...

strip_2369_v4.sch

EAGLE 7.7.0 schematic for the single inverter gate

sch - 290.39 kB - 11/17/2021 at 13:56

See BOM
Download

strip_2369_v4.brd

EAGLE 7.7.0 layout for the single inverter gate

brd - 54.33 kB - 11/17/2021 at 13:55

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  • DCTL

    Yann Guidon / YGDES11/17/2021 at 13:17 0 comments

    DCTL originally meant "Direct Coupled Transistor Logic", as described by @Tim  on his great pages about the CDC6600 technology.

    I have tried to increase the speed/power ratio with the help of a finely tuned base capacitor (C) and a Baker clamp diode (D) which seems to provide a propagation time of 2ns per inverter and/or a much better low-power performance. So this gives a new meaning to DCTL : Diode Capacitor Transistor Logic.

    It's pretty easy to use yet quite unusual because each gate is only an inverter that  provides an open-collector output, so it's all "OR-tied" logic, there is no dedicated inputs for each signal.

    I have presented/introduced the individual gate in the description page of the project:

    I have worked a bit more to make the PCB more compact:

    There is only one via now, and all the passives are on the bottom layer, which could be picl&placed by machines. Here I only use 0603 parts but they could be changed to 0402 or anything you want.

    Here are the top and bottom layouts:

    Now, the Ground/0V rail is on the top layer and directly connected to the PMBT2369's emitter.

    There is some room at the right of the clam diode.

    The bottom layer has the passives (2 cap, 2 res) and the Vcc supply rail.

    I added windows on the rails to make them easier to solder to sources/supplies.

    Overall I have tried to reduce the "height" of the gate, compared to the first version. This makes the strips more densely packed and more cost-effective.

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Discussions

Yann Guidon / YGDES wrote 11/17/2021 at 14:37 point

Looking at my stock:

* BSS84  1K approx. => P-FET
* 2N7002 1 reel (3K) and probably more might be hiding => N-FET

So there is some potential for N-MOST and some CMOS is selected places like bus drivers (to reduce static power)

* BSS65 : 3K PNP 12V
* MMBTA06 : 3K NPN 80V

could replace the 2369 in early prototypes though might not be as fast (not designed for saturation) => the Baker diode clamp will help.

There is also some potential for complementary bipolar gate, maybe TTL ?

Anyway : a full reel of PMBT2369 is about 80-90$ these days. So let's add this, as I ordered a reel:

* PMBT2369 : 3K NPN 15V.

Now another kind of transistor:

* MMBTH81 = MPSH81 in SOT23, 9K × PNP 20V 50mA 600MHz : wanna try some inverted ECL ?
* BFS480 : 8400× dual RF NPN (2xBFR180W) in SOT363, ft=7GHz

These RF transistors don't like the saturated operating modes of older generations so are suitable for ECL. But ECL eats quite a few parts per gate! At least 3×BFS480 for a NOR3. So I can make maybe 2000 to 3000 gates with my stock of BFS480, and 1500 gates with the MMBTH81.

For now, the easiest/cheapest/simplest approach would be to focus on the slow ones, such as the 2N7002, to make N-MOS logic , like the https://megaprocessor.com and design a simple modular system to get something useful in our hands. What about a digital clock ? After all I already have the DFF ! https://hackaday.io/project/9376-yet-another-discrete-clock/log/34817-even-better-10tff

  Are you sure? yes | no

Tim wrote 11/17/2021 at 11:52 point

Maybe you can squeeze the design a bit to get everything to the top so it can be automatically populated?

- route power bus on the bottom

- use smaller solder pads for the THT pins

- use 0402 resistor and cap

- make the schottky diode optional

  Are you sure? yes | no

Yann Guidon / YGDES wrote 11/17/2021 at 12:47 point

I'll provide the EAGLE files and you'll adapt to your manufacture constraints :-)

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Yann Guidon / YGDES wrote 11/17/2021 at 13:59 point

> - route power bus on the bottom

why ? how ?

> - use smaller solder pads for the THT pins
> - use 0402 resistor and cap

you now have the .brd and .sch files, enjoy !

> - make the schottky diode optional

considering its significant performance benefits, well, just omit it from the BOM if you prefer ?

  Are you sure? yes | no

Tim wrote 11/17/2021 at 00:18 point

NAND based RTL should be very efficient on component usage. I am not entirely sure how to handle fan out, though.

I could easily change things to NOR based.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 11/17/2021 at 10:35 point

Look I updated the example of the project description.

Yes, "NOR" is the usual flavour of the DCTL gates (if you remember Thornton's book).

The tricky part is to steer the tools to avoid significant fanout/fanin.

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Tim wrote 11/17/2021 at 12:54 point

https://github.com/cpldcpu/PCBFlow/blob/main/30_PLACE/board_template.brd

This contains RTL part library and JLCPCB design rules

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Yann Guidon / YGDES wrote 11/17/2021 at 13:19 point

Awesome !

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Yann Guidon / YGDES wrote 11/17/2021 at 13:23 point

Oh... I have EAGLE 7.7.0 so this file is incompatible :-/

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Tim wrote 11/16/2021 at 18:40 point

Ok, implemented your logic style into synthesis now. For placement I need to wait until you design the physical layout :)

tim@Eleven:/mnt/d/VHDL/PCBFlow$ ./run_20_Synthesis.sh counter YG
Synthesizing to YG strip logic
note: top entity is "counterx"
13. Printing statistics.

=== main ===

   Number of wires:                 18
   Number of wire bits:             22
   Number of public wires:           4
   Number of public wire bits:       8
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 17
     yg_DFF                          3
     yg_NAND2                        4
     yg_NAND3                        3
     yg_NOT                          7

   Chip area for module '\main': 17.000000

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Yann Guidon / YGDES wrote 11/16/2021 at 18:57 point

I thought it was NOR...

but you can make your own TTL NAND as you like :-D

And I raise my hat to salute your responsiveness ;-)

  Are you sure? yes | no

Tim wrote 11/16/2021 at 18:33 point

I think it would be good to have a DFF as a fixed logic gate. Otherwise they would eat up a lot of real estate.

  Are you sure? yes | no

Yann Guidon / YGDES wrote 11/16/2021 at 18:55 point

Sure but... we have to start somewhere right ? :-D
I'm just trying to get the ball rolling for now.

  Are you sure? yes | no

Tim wrote 11/16/2021 at 18:23 point

So it's breadboardable single gate logic?

Isn't that rather a NAND3 gate?

  Are you sure? yes | no

Yann Guidon / YGDES wrote 11/16/2021 at 18:54 point

It's what you want, I borked the first example, I'll have to re-spin it :-)
And breadboardability is surely a welcome feature though I was thinking of other cases.

  Are you sure? yes | no

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