1 - bit ttl / cmos finite state machine

a finite state machine based on the MC14500 Industrial control unit.

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Using EEPROMS an d-latches to create a 1-bit finite state machine that is
Turing complete. Based very much on the MC14500 Industrial control unit. Currently shelved as the proof of concept build has kind of taken on its own life

This is my CPU project, that was born out of trying to build 1 - bit combination logic ALU's from op-amps.  In doing the research for that project I determined that much of the MC14500 is a relatively simple (still a large number of transistors) finite state machine.    I decided to see if I could build a relatively fast state machine out of EEPROMS and D-Latches. 

This project is very similar, and very much inspired by the UE14500 Vacuum tube computer Project.

My project goals are:

  • Design the logic for the state machine I want to build (this is in it's first draft)
  • Design / build / adapt? a work flow for simply making changes by either building or modifying existing tools for making binaries so that development is less cumbersome.
  • Build a prototype on a breadboard to demonstrate a proof of concept using an 8-bit addressable d-latchs and some switches that can be used to compare 2 8 bit numbers and update a 8-bit display latch.
  • Build a prototype, that is Turing-Complete with expanded functionality for moving 8bit data, jump / return and write a machine language monitor.


a 4 ALU truth table

plain - 160.04 kB - 12/30/2021 at 01:59



a very poorly documented 4 bit alu im trying as a proof of concept.

circ - 24.36 kB - 12/30/2021 at 01:59


1-bit cpu (1 chip logic).circ

logism diagram for the logic which will be replaced by the EEPROM.

circ - 33.28 kB - 11/26/2021 at 03:38


  • Found issues with my innital design, building a proof of concept

    Dave Collins01/04/2022 at 17:28 0 comments

    Ran into several issues, learned a ton on the way; This led to building a 4 bit Proof of concept build based around a different chip the CD4057A.  The plan is to one day re-visit the 1-bit machine with high speed PROMs to make a very fast universal ICU replacement.  I'll post the link to the project page for the 4 - bit machine once it is completed.

  • TSV2HEX is updated

    Dave Collins12/30/2021 at 01:59 0 comments

    fixed 2 bugs, and uploaded a Linux binary tested with a much larger truth table today. A full 4bit ALU with zero, and negative detection.  supports add, subtract 2's compliment, AND, OR and XOR as well as NOT A. additionally there are 2 NO operation Flag states HIGH and LOW which can be used to trigger other signals (or be replaced with more functions). I will be burning a EEPROM this weekend or next for testing. I uploaded the truth table and the Logism files if you would like to try out

  • Tool Chain Completed!

    Dave Collins12/26/2021 at 04:48 0 comments

    I have completed a rudimentary tool chain for building .HEX files from a truth table.  from here I will probably build a proof of concept.  I have not put much thought into what that will look like but non-the less here is the GitHub link for the tool chain.

  • Contemplating 1-bit calculations, and challanges.

    Dave Collins11/26/2021 at 05:37 0 comments

    The Changes to the Instruction set:

    The MC14500 is primarily a 1-bit ICU.  and thus, its not generally meant to do arithmetic (though it can through manual bit manipulation, it's not very fast.)  Just as the UE14500 Project, our CPU will add a Add functions to add and subtract at a cost to some of the less useful functions.  Unlike the UE14500, we will take things a few steps further and add a external command register. This will allow for moving memory and register values around 8 bits at a time, this will be done by adding a OP, code to facilitate switching between the 1-bit state machine and the external command register (which will also be a finite state machine.)

    The MC14500 instruction set is as follows:

    MC14500B Industrial Control Unit Handbook (C) 1977 Motorola Inc.

    Our modified instruction set:

    State Machine modified instruction set

    I've uploaded a preliminary diagram that shows how the logic would be laid out if we were building an actual CPU from gates.  Since this a sate machine we really only care about the truth table, and you can think of this logic diagram only as a guide to how the logic works.  The operation is simple, there is a 4 bit control word that sets how the output bits should output based on the 3 potential bit input lines coming from the 1-bit data bus the Results register, and the Co Register.  The latched registers and flags all update on the falling edge of the clock cycle.  the flags (with acceptation to the CO Input enable signal are generated via a 8 bit multiplexer control word (meaning only 1 flag on the output control register can be enabled at one time.)  The CO enable signal is output separate because it is the only operation that updates both registers at the same time and a multiplexer can only output 1 output based on the 3 bit control word.


    This CPU calculates data 1-bit at a time, though it actually looks at up to 3 bits to make a calculation, 1 bit from each register or the data bus, and a third carry bit stored from the previous operation.    The first challenge of this is there is no real way to do a full subtract operation (at least not 2's compliment, though a 1-bit subtractor is possible, it's not used here).  A full SBA (Subtraction by Addition) operation requires a XOR operation on the carry in bit, but only on the first operation.  In a multi-bit adding scenario this allows for adding a 1 at the same time as adding the compliment of the second operand (to subtract and get a 2's compliment value:

    As you can see the adder will add 1, but invert the inputs on the B input this works simply enough for a multi-bit operation as 4 bits are calculated at once.  However this is slightly inconvenient when we try to do 1 bit operations.  Thisi is simply because we can no longer use the CI line as a mode selection for every bit.  The reason is simple; if we did that the adder would add 1 to each digit (this would not yield 2's compliment).  Instead our CPU will provide 2 operations for arithmetic; add and add compliment.

    This approach is slightly more cumbersome as the CI register has to be preset with a carry in bit (but only once).  then each operation would add the compliment of the B register (when subtracting).  Additionally this adds more functionality to the MU (math unit) as now the add compliment operation can be used to add the inverse of the B register to zero (allowing us to put it's compliment in the results register).

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