A CPU made with 74 series TTL gates, aimed at high performance and simplicity in programming.
The instruction set is highly inspired by MIPS and RISC-V, with only 4 types of instruction encoding, 8 general-purpose registers and 16 bit ALU.
The Chinese ISA manual is now complete! This is an very detailed instruction set manual drafted to resemble an 'official' ISA manual such as that of the RISC-V. The manual is meant to be easy to understand without being too long. Also, another feature of it is that it separates design from implementation. The Dragonfly ISA is designed to be implemented on different platforms, like TTL chips, FPGA, ASIC or even redstone! The manual also talks about how to expand the ISA. All of these means that you can create your own implementation of the ISA, with tweaks that you like! Well, if you can read Chinese... But don't worry, an English version of the manual is coming sooooon!
Although this project has been called Super RISC VII (which is just a joke being 'this ISA is better than the RISC-V') The CPU and ISA actually has no official name! I know in many projects, the CPU, ISA and the project share the same name, I just don't like a big and bulky 3-word name for my CPU. Therefore, I chose 'Dragonfly'. This name actually comes from the ISA's Chinese name, 龙腾. (pronounced like 'Long-teng' or 'Long tum') The characters literally means 'dragon' and 'fly'. Also, this name has a feel of being light, agile and optimized, since that's what dragonflies are, and what this ISA is designed to be.