Operation mode 0 - Read memory contents and emit as Intel HEX format ASCII stream

A project log for Custom circuit testing using Intel HEX files

Download / upload memory contents into computer motherboards or other devices for test or debugging (using 3 micro-coded controllers)

zpekiczpekic 12/08/2021 at 05:470 Comments

The key component in this mode is predictably the Mem2Hex described here. This is how the component is hooked-up:

hexout: mem2hex port map (
            clk => hex_clk,
            reset => reset,
            debug => hexout_debug(15 downto 0),
            nRD => nRead,
            nBUSREQ => hexout_busreq,
            nBUSACK => hexout_busack,
            nWAIT => nWait,
            ABUS => ABUS,
            DBUS => DIN,
            START => button(0),        
            BUSY => LDT1Y,            -- yellow LED when busy
            PAGE => page_sel,        -- select any 8k block using micro DIP switches
            COUNTSEL => '0',        -- 16 bytes per record
            TXDREADY => tx_ready,
            TXDSEND => hexout_send,
            CHAR => hexout_char

Few notes:

Here is how the send character handshake appears in the microcode:

        // "UART" is supposed to signal TDXREADY = 1 when presented 0x00 or when serial trasmit is done
emit:        if TXDREADY then next else repeat;    // sync with baudrate clock that drives UART
        if TXDREADY then next else repeat;
        if TXDREADY then next else repeat;
        if TXDSEND then return else return;

 TDXREADY is checked 3 times in a row to prevent any clock domain glitches. Finally, the TXDSEND is checked, but this condition is hardcoded to "1", means it will always return to the caller at this point, but a simple comparator is hooked up to look for check of this condition to generate the send pulse:

-- hack that saves 1 microcode bit width
TXDSEND <= '1' when (unsigned(m2h_seq_cond) = seq_cond_TXDSEND) else '0';

Sanity check for I/O:

Reading the I/O space can give some indication if it "sniffs right", like in this case. The only IC hooked up to I/O space is 8251 UART, which is enabled when address is XXXXXXXX0001XXXX - when dumping out addresses that match it is visible that "something" appears in those locations, while everywhere else the DBUS returns the default float high.