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The UFS4057ES - A 4 bit ALU / CPU Build

Building a small computer with an EEPROM brain.

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working with the CD4057A as source material, trying to replicate it's core functions using an eeprom. The initial scope is to base it around 12 inputs and 8 outputs, as this is the hard limit of logism. UPDATE: A 13th input line was added due to added functionality in the tool chain.

The CD4057A is a 4 bit ALU Like cos/mos part (early cmos) for use in a LSI computers or control systems of its time and was produced by RCA.   It boasted many features for parallelism, allowing for intelligently stacking multiple units together to create a wide range of bit depths.  It varies somewhat from the 74181, in that it actually has an internal 4 bit shift register with which single bit shifts (across multiple devices).  The shift register can be loaded via a function passed to the chip, and also acts as an internal results register on the falling edge of the clock cycle, making this chip kind of close to a 4-bit cousin of the Motorola MC145000 Industrial control unit. 

In this project, I am attempting to build up a finite state machine in an EEPROM that pay's homage to this chip and tries to mimic it's functions.

using an EEPROM as a basis for the build, it is unlikely to clone the chip entirely. However, using a 4bit latch it may be possible to build many of the chips functions as A FSM (Finite State Machine).  

The proof of concept will be a reduced instruction set chip with only 12 input pins.  The test set up will consist of 2 eeproms (a low word and a high word), two 4 bit d-latches (updating on the falling edge) a pair of 74hc194 parallel shift registers , a ram chip (or another eeprom) to feed code into the ALU a very simple clock circuit and some led's to display the output.        

Schematic_UFS4057ES_2022-01-19.pdf

most up to date schematic, clock module is drawn

Adobe Portable Document Format - 70.54 kB - 01/19/2022 at 17:36

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CD4057A.ods

here is a spread sheet of the control words for the ALU and descriptions of how they work.

spreadsheet - 12.37 kB - 01/18/2022 at 03:56

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decrom.hex

this is the .hex for a very small register decode rom, it handles all of the very simple decode logic for properly updating the 74hc194e universal shift register. again untested.

hex - 88.01 kB - 01/18/2022 at 03:51

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hirom.hex

this is a sample high word rom, with the overlay. it appears to have built properly but yet untested

hex - 88.01 kB - 01/18/2022 at 03:51

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lowrom.hex

this is a sample low word rom, with the overly. it appears to have built properly but yet untested.

hex - 88.01 kB - 01/18/2022 at 03:51

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  • Update to TSV2HEX allows for adding a control line.

    Dave Collins3 days ago 0 comments

    While waiting on parts for the prototype I had some time to work on the software end of the build.  I made a slight change to my eeprom tool chain, and now I am happy to say I can build a .HEX file that supports the full minimum required address lines.  This is due to adding support to overlay the data from another truth table by simply adding the data to the eeprom immediately after the primary data.  The program is still very basic and I will be the first to admit that it probably has a few bugs but at least for the time being it appears that it correctly builds eeproms.  When parts come in in the next week or so I should be able to build a rudimentary proof of concept and run testing.  Additionally, I have drastically re-thought how a 74 series register can be used in the build, and switched to a 74HC194, this allows for performing all shift operations on the register, as opposed to using states within the eeprom.   I believe this will significantly increase the chance of this very tricky to replicate behavior that would require a large number of control lines, or external decode logic to accomplish in the fist place.  Speaking of control logic.  I also built a truth table and spun a small hex file to properly handle much of the decode logic for operating the accumulator register properly.  I have updated the files section with all the newest for your viewing pleasure; if you have any questions don't hesitate to ask

  • Updated Proposed Clock Circut and Simplified Halt

    Dave Collins6 days ago 0 comments

    Here is the updated clock schematic based on suggestions from the Facebook group Z80 DIY/Homebrew Computers & Projects,  I have switched the capacitance values to much lower in order to be able to use larger value timing resistors.  I don't think I mentioned the formula for calculating the frequency is 1.2 / R*C. The main issue with the last schematic is I forgot about the input current limits of the 74HC14N which are around 20mA.  Using a minimum value timing resistor of 275 ohms, is pretty much required to limit the current to the input to a safe state below the current threshold of the input.  Another suggestion was to use a ceramic cap for the R-C networks, since they are less susceptible to temperature change; and with the value much lower a better choice since they are far and away better performing caps, in terms of reliability.  Another change I made was to tie the oscillation low using a transistor. this will halt the clock in full clock mode but leave the ability to single step, which will be useful for the state machine test bed program (you can do a single instruction jump to the next instruction which can augment the halt flag. Still not feeling up to building this up on the bread board, I've ordered 100K trimmers which won't arrive until at least Sunday.  Hope everyone's weekend goes well. 

  • Latched Clock Module without a 555

    Dave Collins7 days ago 0 comments

    I'm nearing completion of the clock module for the prototype and the eventual build. This has 3 main goals:

    1.  No 555 timer. (honestly if your module has a inverter why use a 555). 
    2.  Latch both CLK & ~CLK save the state through a halt and resume sequence.
    3. support a HLT on a HIGH signal from the CPU.

    I completed a first draft of what I'm building in EasyEDA. I have tested most of the module and it works well.   I will need to do further refinements to get it dialed in but its about 90% so I've uploaded a PDF of the working schematic.  You can find it in the files section.


    If you want a latched clock why no 555?

    To be honest; I don't really have a good answer beyond its been over done a million times.  I had initially thought to build a op-amp oscillator but, opted (heh) to do an R-C inverter instead.  The reason is simple; if your non-crystal clock design has an inverter, you should not use a 555, at least in my opinion.

                                                               Simplified R-C Inverter Design

    Here is a over simplification of the clock's main astable oscillator.  The first stage takes the RC oscillation (which appears on the scope as a triangular wave mostly; and outputs a result witch is more or less a rhomboid (and inverted).  Since a waveform that is more or less a parallelogram is going to cause a problem for CMOS High levels, we feed this through a second stage, which flattens out the transitions and we get a nice square wave.  The third stage is more or less just to get a inverted clock, although extra buffering is always nice on the thing you are going to hook to nearly every IC on your build.  With 2 passives ( three when we wire in a trim pot), and 3 more inverters on the other side of the package to de-bounce a single step you can't really go wrong Full R-C Inverter Clock, with single pulse de-bounce.

                                            R-C Inverter clock with a de-bounced single pulse


    In many, many, MCU's with internal oscillators this simple R-C and invert tactic is used. it produces a fairly decent nearly 50% duty cycle, though honestly this can be further refined.  Another advantage to building the clock this way is we get full control of the added ~CLK signal off the output latch.  By way of comparison, the ~Q output of the 555 timer latch is tied to an internal transistor in,  and essentially discharged off to the ground.
     
    We can control the clock selection through a quad buffer (two sets for both ~CLK, CLK, Single Pulse, and ~Single Pulse), and a switch we de-bounce, elsewhere in the circuit. We tie the outputs together using a simple Diode/Resistor setup, in this case only, it's OK to leave the output of the tri-state buffer in tri-state as the OR gates are tied low on their outputs and do not actually care the difference between high Z and  0v (I think).  I build the OR gates this way as two gates from diodes use slightly less tracks, and fewer power rails than a package with two terminated gates, which being in the clock module will likely not find use.

                                                                   ...
    Read more »

  • First draft of .HEX files completed

    Dave Collins01/05/2022 at 19:58 0 comments

      I've completed 2 FSM descriptions in logism, and built source from that. From here, I will burn a pair of eeproms and see how they perform on the bread board with a pair of 4 bit latches.  I expect this to be completed by weeks end but as im working on this in spare time its possible to take longer.

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Dan Maloney wrote 01/12/2022 at 00:52 point

Wow, that's quite a dinosaur of a chip! Where did you find something like that?

  Are you sure? yes | no

Dave Collins wrote 01/12/2022 at 01:33 point

It's actually someone else's picture, that's how hard it is to find. I do have a line out on a few group lots. Finding a functional one is hard ... Its one of the drives to build this project up.  I know of one or two warehouse lots available but very sketchy web sites. I'd really like one to compare performance. Honestly the only application I have even read about is ground based radar units.  So it's definitely a rare find. 

  Are you sure? yes | no

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