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The UFS4057ES - A 4 bit ALU / CPU Build

Building a small computer with an EEPROM brain.

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working with the CD4057A as source material, trying to replicate it's core functions using an eeprom. The initial scope is to base it around 12 inputs and 8 outputs, as this is the hard limit of logism. UPDATE: A 13th input line was added due to added functionality in the tool chain.

The CD4057A is a 4 bit ALU Like cos/mos part (early cmos) for use in a LSI computers or control systems of its time and was produced by RCA.   It boasted many features for parallelism, allowing for intelligently stacking multiple units together to create a wide range of bit depths.  It varies somewhat from the 74181, in that it actually has an internal 4 bit shift register with which single bit shifts (across multiple devices).  The shift register can be loaded via a function passed to the chip, and also acts as an internal results register on the falling edge of the clock cycle, making this chip kind of close to a 4-bit cousin of the Motorola MC145000 Industrial control unit. 

In this project, I am attempting to build up a finite state machine in an EEPROM that pay's homage to this chip and tries to mimic it's functions.

using an EEPROM as a basis for the build, it is unlikely to clone the chip entirely. However, using a 4bit latch it may be possible to build many of the chips functions as A FSM (Finite State Machine).  

The proof of concept will be a reduced instruction set chip with only 12 input pins.  The test set up will consist of 2 eeproms (a low word and a high word), two 4 bit d-latches (updating on the falling edge) a pair of 74hc194 parallel shift registers , a ram chip (or another eeprom) to feed code into the ALU a very simple clock circuit and some led's to display the output.        

Schematic_UFS4057ES_2022-05-19.pdf

most recent schematic - last upload only had the ALU module

Adobe Portable Document Format - 335.22 kB - 05/19/2022 at 21:55

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CD4057AD - RCA COS-MOS Components 1975.pdf

Best Datasheet i can find for the original part, from the RCA components catalog 1975

Adobe Portable Document Format - 734.58 kB - 05/08/2022 at 04:18

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523-00553-0-W27E257.pdf

EEPROM Datasheet

Adobe Portable Document Format - 227.00 kB - 05/08/2022 at 04:18

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CD4057A.ods

here is a spread sheet of the control words for the ALU and descriptions of how they work.

spreadsheet - 12.37 kB - 01/18/2022 at 03:56

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rcl.hex

Register Control adds Zero and flag's update

x-hex - 88.01 kB - 05/08/2022 at 04:28

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  • Simple PCB Power Supply the PCBWay...

    Dave Collins05/07/2022 at 04:59 0 comments

    So for a while now I've wanted to build a small power supply for the ALU project.  I really didn't want to spend a ton of time laying one out, and I didn't want to loose a ton of focus specifically working on the power supply because, I feel like I have a good clip on the ALU build.   So stumbled across this project on CurcutDigest its simple; slightly sketchy, but it works.  

    About a week or two ago, this project started picking up some steam, and it found some notice with the folks over at PCBWay! They had offered to supply the PCB's if I would review their services.  I've already used their services on some of my other projects, and have already been very happy before so I saw no issue putting this together for them.

    First, the process was simple, just uploaded the Gerber files, clicked a few buttons selected a color and before I knew it the boards were on the way.  It took about a week, using standard shipping the total cost with shipping came to about 20 dollars, for 5 boards, had I paid for them.   Honestly for rapid turn PCB prototyping, the price is reasonable and competitive for the quality that you get.  I've used a few different companies to have this done, and the quality PCBWay, for the cost, is hard to beat.

    Lets talk about the CurcutDigest DIY Breadboard power supply:

    The power supply is very simple, it uses a standard 8705 linear voltage regulator. and also has space for a LM317 Variable voltage regulator which can be configured for a second voltage, the design specifies values for a 3.3v regulated supply.  

    In my case I only built up the 5 volt side, and power LED.  I also replaced the jumper blocks with 1 side of a few latching SPDT switches.  The key to this configuration was making sure the switch covers the expected current for the circuit, in my case I think  I am  fine but it's something to watch if you want to try this mod.  The nice part is you can use the latching switch to turn the power on and off from the board quickly without unplugging the supply from the wall.

    Issues and complications:

    When I built this supply Initially I had to start over on a new board because I tired to use a tip that was too small for the large ground planes, which cover both sides of the board; along with trying to use lead free solder that was still set up in my station. the results were not pretty:

    I ran into some real issues with the very small modern through hole capacitor footprint, this resulted in some very poor soldering and i ended up damaging a regulator.  I switched to a larger flat tip, with some 60/40 solder and everything went much better.  The boards were also HASL finish, and I've had some issues with fine soldering trying to use mismatched solders like that, its 100% an error in judgement on my part, and not the blame of the board making process.   

    Another issue I ran into is:   

    The ground pin for the power LED, pictured here is towards the inside of the board 

    But as you can see, the silk screen is backwards.  This is an issue with the PCB layout and not the manufacture, and another think to keep in mind if you build this board up, you have to install the LED in backwards, according to the silk screen. 

    Mechanically, the board could use another row of output bergstick pins, I think that would stabilize the connection to the board a bit better, with this set up I have to prop something under the supply so it doesn't fall off the end of the board. This might also be 100% my fault to begin with, as I have relatively cheep breadboards.

    as you can see by the design, there is no heat sync on the regulator, and there's no protection diode, just simply the regulator and a few ceramic caps. Maybe at another time I can correct the schematics, and add some simple preventative measures...

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  • ALU Deep Dive

    Dave Collins05/04/2022 at 19:23 0 comments

    So This week I wanted to do a more in depth look at the ALU unit I have been building up. And since I didn't really get a chance to do a full deep dive post last weekend, This week there are two!  In addition I have Partnered with PCBWay on a small power supply for the breadboard CPU which I'll be doing an exclusive build write up, PCB's designed over at CircutDigest.  Its not my design but I needed something simple moving forward and I've been wanting to build something like this for a while now.  PCBWay has kindly offered to cover the costs of prototyping for that project if ill do a small write up on my experience with their services, so if after you take a look at this why not head on over to my main project page, where you can find the write up on the power supply project. With that sorted, wanted to take some time to talk about the main attraction, the State Machine ALU.  

    Here it is pictured above.  The module with the three EEPROMS is the state machine. The ALU's logic is 100% comprised of 32K eeproms (w27e257 specifically) :

    These chips are inexpensive, available as pulls/used, and mostly available from the usual sources such as EBAY / Amazon (I've had good luck so far but your mileage may vary). 

    Using an EEPROM as a state machine is not new, but in these times finding parts for an actual PLA is getting interesting.    In this case EEPROMS fit the bill nicely.  Additionally I have a TL866 microchip programmer witch works out of the box at the 12v programming voltage these less desirable chips require. 

    The Schematic for the ALU is fairly simple, I've re-labeled the inputs on the parts in EasyEDA to make the schematics more readable.  The first two EEPROMS take care of the actual operations, while the third performs register and flag control.  This absolutely could have been further simplified by using a 16 bit EEPROM for more states, but 32k EEPROMS are what I had on hand.  When there's a chip shortage you kind of have to work with what you have. You'll note there's still two whole address lines unused on the main logic EEPROMS.   Initially this was due to the 12 input limit Logism has for building a truth table, I later expanded it to 13 using some trickery in my tool chain to merge two truth tables together. the remaining two inputs are wasted, for the time being but could not really be efficiently used due to that limitation.  That being said, I am planning on switching to Digital Logic simulator but I haven't tested this simulator to determine the limits for truth tables but this looks promising.

    Each 4 bit unit is tied directly to the registers outputs before the bus transceiver.  Its important to remember the EEPROMS always compare the registers regardless of the state of the clock (unless the EEPROM is placed in cut off by puling /ALI high.)  The output writes directly to the input of the accumulator on the falling edge of the clock.  This is of course a function of the universal shift registers which make up the accumulator module we've discussed elsewhere.  

    The two 4 bit units are different in a few ways and they all have to do with the arithmetic functions. Looking at the original COS-MOS part, we can see how the original compares to the state machine. 

    SOURCE: 1975 RCA COS-MOS Digital Circuits

    As you can see there are VDD/VSS pins on this and most COS-MOS parts, this was as i understand it (and somebody please correct me if I am wrong), in order to establish a high / low range for the part. The TTL/CMOS ROMS are only 5v but the original parts had a much wider input range. The indicator outputs are all covered under a more simplified single flags made on the main ROMS, and flag update signal made in the register control ROM. Zero is handled by all three ROMS with the two zero operations being checked by a logical AND in...

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  • Quick mid week update

    Dave Collins04/28/2022 at 02:27 0 comments

    I've uploaded some new files: New logisim design, which includes a slightly updated register control.  Additionally the files that correspond to that EEPROM and finally a new schematic including the ALU module and a quick and dirty layout and PCB for a regulated breadboard power supply, from Circuit Digest. I plan to do a full build and reflection entry as soon as I have PCB's at hand; this will include a video with a part by part soldering (if you like that sort of thing ).  The PCB is very simple, Cheep and effective and its far and away better than my current hot wired USB cord and transformer set up. Hope to have some exciting news (well for me at least ) to go along with that next segment.  By weeks end I should be cutting jumpers for the ALU, the rom's burnt perfectly so hopefully if the build goes fast I can do some actual tests with the accumulator.

  • Accumulator and Data Bus Register are complete (A&B Registers)

    Dave Collins04/19/2022 at 00:25 0 comments

    I've completed building up both the data bus storage, and the accumulator registers.  Both designs were developed to be very similar to the Ben Eater / SAP - 1 style register module.  The two registers are slightly different, so I thought i'd try to explain my thought process here for each of them.

    Bus Control

    Each is separated from the main bus with a SN74HC245E bus transceiver; which is used to enable the register output. 


    A logic low signal is required by this package's output enable that will likely require an inverter to control the signal from the module handling the micro-coded instruction set; as its likely the EEPROM may have an issue driving the signal low, even with the weak pull-up.  This will need to be a consideration for that module when I finally get around to building it.  On the accumulator (pictured above)  the data bus is only connected to the transceiver output, however on the storage register it is connected to both the transceiver output and the input of the d-latch which is used in that module.  This was done, as the CD4057 has an internal shift register which can only be updated by the ALU via a control word; it is not directly wired to the bus.  The Data storage register however is, and can be updated via the main bus or output its contents onto the bus. I've tied the direction in a fixed state B -> A, and tied the output by default to high Z, so that when the /AOE or /BOE signals are not present from the control module the register is in high Z. Additionally input enable signal on the storage register must also be enabled for the register to accept a clock tick, so when it is not enabled the register is effectively in tri-state.

    Latch package types: 

    The latches for the registers themselves are either constructed from  74HC194E universal 4 bit shift registers, or 74HC175E quad D-Latches.  The a pair of shift registers make up the accumulator: 

    This will require some decode logic on the part of the ALU to set S0 and S1 (which change the store or shift function of the register. Additionally, other logic will be required to detect and return a carry bit in the case of a rotation operation. currently this is built as an eeprom; but the logic is so simple I may switch to building this as discrete logic; or a low pin output high speed prom.  The advantage to using a shift register is that it saves on states in the eeprom for handling the rotation and shifting functions, as well as drastically simplifying the truth table.   The B register on the other hand, uses a pair of quad d-latches and an and gate: 

    An enable signal was added by a logical AND gate with the falling edge of the clock.  This allows the register to simply drop the clock pules which are not significant to updating the latch allowing us to simply attach the main bus directly to the latch.  This was necessary as the quad d-latch always outputs its stored value, and always updates on the rising edge of  what ever clock pulse comes in. Lastly updates to this register will be through the system bus and configured by the control module.

    Conclusion and what's next: 

    Now that the registers are set up, we are ready to move on to the actual ALU and a very rudimentary control logic.  As always I've updated the complete schematics of what I'm working on, and those can be located in the files section of the hack a day page.  For more updates, you can always watch this space or check out the myriad Facebook groups I frequent. Particularly Minimalist Computing, lately.  I hope you all had a pleasant week, and I hope to update this space with more as more details reveal themselves.

  • Clock module deep dive

    Dave Collins01/24/2022 at 05:10 0 comments

    Introduction and explanation:

    In the current project version of the clock module I wanted to have a clock module that had a fairly stable state, that had clean /CLK and CLK transitions (with no delay between the inverse and non-inverse state of the clock) both heaving a 50% duty cycle.  Also, I needed to be able to half step through a clock cycle in order to see the data states at the high to low (and low to high transition).  The main reason for this is the accumulator register is compared with the data bus on the rising edge in the ALU and clocked into the accumulator latch on the falling edge ( replacing the previous value from the latch, which was used by the ALU during the rising edge. ) 

    excuse the poorly drawn paint slide

    These transitions ideally will happen thousands or even millions of times in a second, and so it's important to have a clock that can properly supply carefully timed rising edges where we need them in order to facilitate  these calculations without running into trouble.  If we use a simple inverter on the clock from a 555 timer, when we being to run tests at faster speeds the propagation delay becomes significant.   The solution is simple, generate both clock pulses simultaneously and eliminate the delay.   We can do this many ways, using two parallel XOR gates, buffering the clock with similar parts , or as I've done use a clock divider and only focus on the rising edge of the clock. By latching the clock with a D-Latch, we assure a 50% cycle by only worrying about 1 thing, the rising edge of the incoming clock pulse.
    divide the unlatched clock  and the outputs are 1/2 the input, as the state of Q flips on the rising edge of CLK

    The incoming clock pulse can be at any duty cycle, and the resulting output will be based on the rising edge of the incoming clock pulse only.   This has the advantage of generating a output that is exactly 50% of a duty cycle based on that rising edge, likewise the rising edge of /CLK is exactly at the same time as the falling edge of CLK.    This has the glaring issue of reducing the incoming result from the oscillator by half, we can overcome this issue by building an oscillator that is twice as fast as we need.

    R-C inverter Circuit

    The resistor R11, and Trimmer R10 (combined with C7) provide the R-C network that makes up the main oscillator, as you can see this is essentially two Schmidt Trigger inverters tied together, the first with the resistors connected in feedback to create a very simple square wave oscillator.   As I've discussed in previous Logs, this is a very common configuration for building an internal oscillator in a MCU, and has the benefit of being very "Parts Light".  The reaming nets on the chip are used for generating Power On Reset (C1, R6 and ZD1), half step pulse (technically a single pulse generated by R9 and C3), and a de-bounced switch for the function select latch (C4 and R8).

    the formula for frequency calculation is 1/RC ( in this case 2hz - 1.4khz ~ I did later end up using values to tune the eventual output to 2hz and 2khz -- though this came down to playing around with the values to find ones that produced this output.)

    The power on reset signal, is simply a R-C circuit with a ziener diode that assures the signal is not sent to the inverter until it is at least 4.7v (de-triggering the input to a much higher threshold.)   This has the added benefit of dropping the CPU into a continual reset state if the V+ rail drops below 4.7v in the case of a near over current situation.

    Function  Select Buffer

    The function select is simply a Quad buffer package, the signals Clk.ON and Sp.ON are generated elsewhere (using a latch).   The buffer holds both the Unlatched clock signal, and the single pulse clock in High-Z, using the pull up resistors at pins 1 and 13.  We tie these signals low using a d-latch and it's Q and /Q outputs.  The cumulative...
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  • Clock module completed schematics uploaded

    Dave Collins01/22/2022 at 04:55 0 comments

    A longer explanation of the completed clock module is forthcoming.  A brief technical description of the module is available in the PDF of the schematics.  For now the module:

    • keeps track of the state through transitions using a d-latch connected as a clock divider
    • switches between states using a single push button.
    • sends a momentary power on reset signal
    • accepts a high signal which when held high, the clock stops ( and holds it's state)
    • does not use a NE555 Timer.

    This is done with only 3 chips.

  • Update to TSV2HEX allows for adding a control line.

    Dave Collins01/18/2022 at 03:50 0 comments

    While waiting on parts for the prototype I had some time to work on the software end of the build.  I made a slight change to my eeprom tool chain, and now I am happy to say I can build a .HEX file that supports the full minimum required address lines.  This is due to adding support to overlay the data from another truth table by simply adding the data to the eeprom immediately after the primary data.  The program is still very basic and I will be the first to admit that it probably has a few bugs but at least for the time being it appears that it correctly builds eeproms.  When parts come in in the next week or so I should be able to build a rudimentary proof of concept and run testing.  Additionally, I have drastically re-thought how a 74 series register can be used in the build, and switched to a 74HC194, this allows for performing all shift operations on the register, as opposed to using states within the eeprom.   I believe this will significantly increase the chance of this very tricky to replicate behavior that would require a large number of control lines, or external decode logic to accomplish in the fist place.  Speaking of control logic.  I also built a truth table and spun a small hex file to properly handle much of the decode logic for operating the accumulator register properly.  I have updated the files section with all the newest for your viewing pleasure; if you have any questions don't hesitate to ask

  • Updated Proposed Clock Circut and Simplified Halt

    Dave Collins01/14/2022 at 20:31 0 comments

    Here is the updated clock schematic based on suggestions from the Facebook group Z80 DIY/Homebrew Computers & Projects,  I have switched the capacitance values to much lower in order to be able to use larger value timing resistors.  I don't think I mentioned the formula for calculating the frequency is 1.2 / R*C. The main issue with the last schematic is I forgot about the input current limits of the 74HC14N which are around 20mA.  Using a minimum value timing resistor of 275 ohms, is pretty much required to limit the current to the input to a safe state below the current threshold of the input.  Another suggestion was to use a ceramic cap for the R-C networks, since they are less susceptible to temperature change; and with the value much lower a better choice since they are far and away better performing caps, in terms of reliability.  Another change I made was to tie the oscillation low using a transistor. this will halt the clock in full clock mode but leave the ability to single step, which will be useful for the state machine test bed program (you can do a single instruction jump to the next instruction which can augment the halt flag. Still not feeling up to building this up on the bread board, I've ordered 100K trimmers which won't arrive until at least Sunday.  Hope everyone's weekend goes well. 

  • Latched Clock Module without a 555

    Dave Collins01/14/2022 at 04:40 0 comments

    I'm nearing completion of the clock module for the prototype and the eventual build. This has 3 main goals:

    1.  No 555 timer. (honestly if your module has a inverter why use a 555). 
    2.  Latch both CLK & ~CLK save the state through a halt and resume sequence.
    3. support a HLT on a HIGH signal from the CPU.

    I completed a first draft of what I'm building in EasyEDA. I have tested most of the module and it works well.   I will need to do further refinements to get it dialed in but its about 90% so I've uploaded a PDF of the working schematic.  You can find it in the files section.


    If you want a latched clock why no 555?

    To be honest; I don't really have a good answer beyond its been over done a million times.  I had initially thought to build a op-amp oscillator but, opted (heh) to do an R-C inverter instead.  The reason is simple; if your non-crystal clock design has an inverter, you should not use a 555, at least in my opinion.

                                                               Simplified R-C Inverter Design

    Here is a over simplification of the clock's main astable oscillator.  The first stage takes the RC oscillation (which appears on the scope as a triangular wave mostly; and outputs a result witch is more or less a rhomboid (and inverted).  Since a waveform that is more or less a parallelogram is going to cause a problem for CMOS High levels, we feed this through a second stage, which flattens out the transitions and we get a nice square wave.  The third stage is more or less just to get a inverted clock, although extra buffering is always nice on the thing you are going to hook to nearly every IC on your build.  With 2 passives ( three when we wire in a trim pot), and 3 more inverters on the other side of the package to de-bounce a single step you can't really go wrong Full R-C Inverter Clock, with single pulse de-bounce.

                                            R-C Inverter clock with a de-bounced single pulse


    In many, many, MCU's with internal oscillators this simple R-C and invert tactic is used. it produces a fairly decent nearly 50% duty cycle, though honestly this can be further refined.  Another advantage to building the clock this way is we get full control of the added ~CLK signal off the output latch.  By way of comparison, the ~Q output of the 555 timer latch is tied to an internal transistor in,  and essentially discharged off to the ground.
     
    We can control the clock selection through a quad buffer (two sets for both ~CLK, CLK, Single Pulse, and ~Single Pulse), and a switch we de-bounce, elsewhere in the circuit. We tie the outputs together using a simple Diode/Resistor setup, in this case only, it's OK to leave the output of the tri-state buffer in tri-state as the OR gates are tied low on their outputs and do not actually care the difference between high Z and  0v (I think).  I build the OR gates this way as two gates from diodes use slightly less tracks, and fewer power rails than a package with two terminated gates, which being in the clock module will likely not find use.

                                                                   ...
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  • First draft of .HEX files completed

    Dave Collins01/05/2022 at 19:58 0 comments

      I've completed 2 FSM descriptions in logism, and built source from that. From here, I will burn a pair of eeproms and see how they perform on the bread board with a pair of 4 bit latches.  I expect this to be completed by weeks end but as im working on this in spare time its possible to take longer.

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zpekic wrote 04/29/2022 at 06:08 point

Love to see old devices brought back to life! I wonder if the equivalent function would fit into a GAL22V10... 

  Are you sure? yes | no

Dave Collins wrote 04/29/2022 at 10:36 point

Actually, was thinking about CPLD, always wanted to learn. At some point I'm looking toward making a pin compatible replacement, with some enhancement. 

  Are you sure? yes | no

zpekic wrote 04/29/2022 at 17:34 point

That would be a fun project! I saw some here even making their own chips. A generic "mux+ALU+reg" chip could be a great building block for so many homebrew CPU projects. 

  Are you sure? yes | no

Dave Collins wrote 04/29/2022 at 18:33 point

I think so, I am hopeful to work towards a standard "modern" LSI ALU and peripherals set for hobbyists.  Also I would really like to get better at computer design and that mainly why I am doing this as a fun learning hobby.

  Are you sure? yes | no

Ken KD5ZXG wrote 04/22/2022 at 20:01 point

The issue with memory of any kind faking logic is that ALL address inputs have to be held valid, or ALL outputs glitch. I dunno about a two phase system, seems like asking for problems. But a three phase system of addressible register memory > addressible alu table memory > non-addressible latch > addressible register memory. Latch in the cycle allows for invalid glitch without harm. Everspin offers parallel MRAM with 21 inputs and 16 outputs if you ever want to play with huge ALU or state machine tables or go 35nS fast. Consider redundant mirror written register memories (cheap 32Kx8 even if underfilled), so A vs B can be read simultaneously and ambidextrously. 

  Are you sure? yes | no

Dave Collins wrote 04/22/2022 at 22:50 point

So I'm convinced the speeds I plan to run on the breadboard will allow ample time for the lines to settle, I have in the back of my mind to bring the whole project over to CPLD at the very least the accumulator and the ALU. I think it will be required to run the part at speeds over the 1kHz I am testing at currently. Of course there is a level of ridiculousness that almost requires I hook this thing up to a 7mhz or even 16mhz crystal just to watch it all fall apart on the scope. But that's part of the fun no?

  Are you sure? yes | no

Ken KD5ZXG wrote 04/23/2022 at 10:57 point

Are S and W (Sign and MSB) always same? If so, count one less output...

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Dave Collins wrote 04/29/2022 at 18:39 point

subtraction is 2's compliment, in this configuration; though the original part is not specifically tied in to this.  Because its an ALU and it outputs overflow, carry and negative flags it's significance can be determined by the programmer / system designer. in this case i'll have a 4 bit flags register (built later) that can be read by op-code and conditional jumps.

  Are you sure? yes | no

Dan Maloney wrote 01/12/2022 at 00:52 point

Wow, that's quite a dinosaur of a chip! Where did you find something like that?

  Are you sure? yes | no

Dave Collins wrote 01/12/2022 at 01:33 point

It's actually someone else's picture, that's how hard it is to find. I do have a line out on a few group lots. Finding a functional one is hard ... Its one of the drives to build this project up.  I know of one or two warehouse lots available but very sketchy web sites. I'd really like one to compare performance. Honestly the only application I have even read about is ground based radar units.  So it's definitely a rare find. 

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