In the current project version of the clock module I wanted to have a clock module that had a fairly stable state, that had clean /CLK and CLK transitions (with no delay between the inverse and non-inverse state of the clock) both heaving a 50% duty cycle. Also, I needed to be able to half step through a clock cycle in order to see the data states at the high to low (and low to high transition). The main reason for this is the accumulator register is compared with the data bus on the rising edge in the ALU and clocked into the accumulator latch on the falling edge ( replacing the previous value from the latch, which was used by the ALU during the rising edge. )
excuse the poorly drawn paint slide These transitions ideally will happen thousands or even millions of times in a second, and so it's important to have a clock that can properly supply carefully timed rising edges where we need them in order to facilitate these calculations without running into trouble. If we use a simple inverter on the clock from a 555 timer, when we being to run tests at faster speeds the propagation delay becomes significant. The solution is simple, generate both clock pulses simultaneously and eliminate the delay. We can do this many ways, using two parallel XOR gates, buffering the clock with similar parts , or as I've done use a clock divider and only focus on the rising edge of the clock. By latching the clock with a D-Latch, we assure a 50% cycle by only worrying about 1 thing, the rising edge of the incoming clock pulse.
The incoming clock pulse can be at any duty cycle, and the resulting output will be based on the rising edge of the incoming clock pulse only. This has the advantage of generating a output that is exactly 50% of a duty cycle based on that rising edge, likewise the rising edge of /CLK is exactly at the same time as the falling edge of CLK. This has the glaring issue of reducing the incoming result from the oscillator by half, we can overcome this issue by building an oscillator that is twice as fast as we need.