The memory map

A project log for MRC6502 - Modular Retro Computer

MRC6502 is a fantastic opportunity to learn more about digital electronics and 6502 assembly programming... step by step.

padnestpadnest 01/24/2022 at 11:250 Comments

I designed the system memory mapping with these purposes in mind:

Memory layers: 

Memory configurations

Bus lines EROM1 and EROM2 are used to enable or disable ROM layers: disabling the ROM you can read from the background RAM.

These lines can be programmatically controlled by one of the VIAs port.

Each I/O device has 256 memory locations (one page) of space to map internal registers.

ROM banking

Since the ROM size is 32Kb we can have four 8Kb banks and so two different versions of ROM.

Bus line ROM14 is used to select which ROM locations are visible at the assigned ROM spaces. 

Also ROM14 can be programmatically controlled by one of the VIA port (this might be a bit tricky to do at runtime!).

Glue logic

To implement all the chips selection logic just a single IC will be used: a programmable logic device (PLD).

This choise has many advantages (reduced number of components, easy to make changes, space optimization).

The PLD (an Atmel ATF22V10C) will be programmed following this table:

Inputs signals:

Output signals:

Next step: CPU board.