Timings #1 - CPU vs RAM&ROM

A project log for MRC6502 - Modular Retro Computer

MRC6502 is a fantastic opportunity to learn more about digital electronics and 6502 assembly programming... step by step.

padnestpadnest 01/29/2022 at 07:510 Comments

Timings are crucial! Let's check if we can go with a 4MHz clock using 70nS SRAM and the EEPROM.

CPU timings

First of all I want to try to recap CPU informations about timings from the WDC W65c02s datasheet.  

In the picture:

Let's zoom now into PHI2 HIGH phase:

It's very important to observe what happens after the PHI2 HIGH-to-LOW transition:

PLD delay

PLD, as you already know now, handles all the glue logic; there is a propagation delay introduced by the ATF22V10C-15 (max 15nS) but this should have no practical effects on timings.

RAM timings

In the next picture:

(almost ***): can we have problems when RAM CE goes HIGH but CPU is still reading for additional 10nS?

From RAM datasheet:

When CS goes HIGH the RAM hold valid data for tCHZ time that should be from 0nS to 25nS so we need to test RAM access @4Mhz to verify if this is true and if it can be a real or a pratical problem.

Perhaps the PLD propagation delay (15uS) could save us here, I don't know... (tests are required).

EEPROM timings

Let's check now the AT28C256-15 EEPROM:

I have to update the PLD glue logic table applying the changes in red:

Next step: RAM/ROM test on access

Let me know what do you think in the comments...



I would like to thank everyone who sent join requests for the project. I'm considering whether or not to accept some collaborations maybe a little further on. Commenting on posts is already a way to collaborate and to help me. Many many thanks!