MOV instructions are copying data between registers in CPU.

All MOV instructions are taking up a single word, and need one clock cycle to fetch and one to execute.

When multi-word flag is set, several consecutive registers can have their contents copied to other group of consecutive registers with one instruction. In this case, there is one clock cycle for fetch, and a number of clock cycles to execute, corresponding to the number of registers moved.

Regular Move (MOV)

There are 2 register files in CPU: General Purpose Registers (GPR) and Memory Pointers (MP), and therefore there are 4 types of register transfers: GPR -> GPR, GPR -> MP, MP -> GPR and MP -> MP.

              Instruction bits
Mnemonic:     F E D C  B A 9 8  7 6 5 4  3 2 1 0
MOV rB rA     0 0 1 1  0 d d d  s s s 0  0 x x x    move GPR to other GPR
MOV mpB mpA   0 0 1 1  1 d d d  s s s 1  0 x x x    move MP to other MP
MOV mpB rA    0 0 1 1  1 d d d  s s s 0  0 x x x    move GPR A to MP B
MOV rB mpA    0 0 1 1  0 d d d  s s s 1  0 x x x    move MP A to GPR B

s - bits of source register address(A), where data is coming from
d - bits of destination register address(B), where data is written to
x - "don't care" bits - have no effect on result
A, B - numbers in range 0-7, they are register addresses

Both GPR and MP are numbered 0 through 7, so there are 2 sets of 8 registers. To disambiguate between them, bits B and 4 are used for destination and source respectively. If disambiguating bit is 0, the GPR is addressed, if it is 1, then it is MemPointer.

Special Move (MOVs)

Bit 3 indicates register transfers to additional registers, such as MDB, IVB, and SR.

Bit 2 indicates transfer direction -- 0 = read special reg, 1 = write special reg.

Bits 0 and 1 are used as address of special registers.

              Instruction bits
Mnemonic:     F E D C  B A 9 8  7 6 5 4  3 2 1 0
MOVs rB SR    0 0 1 1  d d d d  x x x x  1 0 0 1    move SR to rA
MOVs SR rA    0 0 1 1  x x x x  s s s s  1 1 0 1    move rA to SR
MOVs rB MDB   0 0 1 1  d d d d  x x x x  1 0 1 0    move MDB to rA
MOVs MDB rA   0 0 1 1  x x x x  s s s s  1 1 1 0    move rA to MDB
MOVs rB IVB*  0 0 1 1  d d d d  x x x x  1 0 1 1    --  cannot read IBV
MOVs IVB rA   0 0 1 1  x x x x  s s s s  1 1 1 1    move rA to SR

s - bits of source register address(A), where data is coming from
d - bits of destination register address(B), where data is written to
x - "don't care" bits - have no effect on result
A, B - numbers in range 0-7, they are register addresses

General layout of instruction types