Mackerel-08
Based on the original prototype hardare, this SBC combines the 52-pin PLCC MC68008, a 512KB EEPROM, up to 3.5MB of SRAM, and a XR68C681 DUART on a single PCB. The DUART exposes two serial ports and three bit-banged SPI headers. One of these headers is currently used with an SD card breakout board to provide bulk storage to the system.
Three 22V10 PLDs are used for address decoding, interrupt mapping, and DTACK generation respectively. An expansion header breaks out address, data, and control lines to allow additional peripherals to be connected directly to the processor bus.
Although the CPU is rated to 10 MHz, Mackerel runs reliably with an overclock to 16 MHz.
The address space is mapped as follows:
RAM: 0x000000 - 0x37FFFF (up to 3.5 MB)
ROM: 0x380000 - 0x3FBFFF (496/512 KB usable)
DUART: 0x3FC000 - 0x3DFFFF (8KB)
Exp: 0x3FE000 - 0x400000 (Expansion header, 8KB)
Mackerel-08 uses a 74HC595 shift register to create a BOOT signal for the first eight /AS cycles of the CPU after reset. This BOOT signal is used by the address decoder PLD to map the ROM to address 0x000000 long enough for the CPU to read the initial stack pointer and program counter vectors from ROM. RAM is mapped to 0x000000 after that.
Mackerel-10
Mackerel-10 is the second phase of the project and the hardware is in development. It expands the design of Mackerel-08 with a full-size MC68010 CPU and 16-bit databus. Additionally, it dramatically increases the memory capacity with a DRAM controller implemented in a CPLD and up to 16 MB of 30-pin SIMM DRAM. Storage capabilities are expanded with an IDE header for a harddrive or CF card.
The software provides the ability to set the system clock using the NMEA data stream and display the receiver's position. It can also configure the NMEA data stream to support running an NTP daemon for long-term time synchronization, but your current application does not require this functionality.