What's all this myHDL stuff, anyhow?

The purpose of this project is to teach myself myHDL and creating some useful cores in the process.

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This project is my learning log that documents my progress wrapping my head around the Python library named myHDL created by Jan Decaluwe. His Python module pretty much turns Python into an open source digital hardware development/verification suite. If you are not appalled by the idea of using an easy to learn language to model and verify digital hardware, you should check this module out, it's fun.
I'm neither a digital hardware designer nor an experienced Python user, so there might be a bumpy road ahead. On the other hand, since I'm kind of a python/myHDL-noob myself, I'll be using a straight forward approach to get my cores to work, so other beginners like me might use this log to dip their foot into the vast ocean which is digital design / myHDL without being scared by too much black magic technique. Sources are on my github.

Installation and configuration of the myHDL dev tools (Ubuntu 16.04)

I'll provide a virtualbox image with all the tools and sources to avoid wasting time solving problems arising from working with different toolsets/configs. The installation steps I took for this image are the following:

  1. Installation of git
    sudo apt install git
  2. Creating a local git folder
    mkdir ~/gitprojects
  3. Changing into that folder...
    cd ~/gitprojects
  4. Cloning the most recent myHDL version
    git clone
  5. Cloning the most recent myHDL_shenanigans version
    git clone
  6. Installation of pip
    sudo apt install python-pip
  7. Installation of virtualenv
    pip install virtualenv
  8. Updating of pip
    pip install --upgrade pip
  9. Make a new directory for the python virtual environments
    mkdir ~/pyvirenv && cd ~/pyvirenv
  10. Create a new virtual environment for myHDL1.0dev
    virtualenv myhdl10dev
  11. Activate this virtual environment
    source ~/pyvirenv/myhdl10dev/bin/activate
  12. Change into the myhdl folder and Install myhdl1.0dev into our virtual python environment
    cd ~/gitprojects/myhdl/ && python install
  13. Install GTKwave
    sudo apt install gtkwave
  14. Install Pillow
    pip install Pillow
  15. Install numpy
    pip install numpy
  16. Install project icestorm ( original source )
    1. Prerequisites
      sudo apt install build-essential clang bison flex libreadline-dev gawk \
      tcl-dev libffi-dev git mercurial graphviz xdot pkg-config python python3 \
    2. IceStorm Tools ( icepack, icebox, iceprog, icetime, chip database )
      cd ~/gitprojects
      git clone icestorm
      cd icestorm
      make -j$(nproc)
      sudo make install
    3. Arachne-PNR ( the place & route tool )
      cd ~/gitprojects
      git clone arachne-pnr
      cd arachne-pnr
      make -j$(nproc)
      sudo make install
    4. Yosys ( Verilog synthesis )
      cd ~/gitprojects
      git clone yosys
      cd yosys
      make -j$(nproc)
      sudo make install
  17. Creating a .rules file to access a Lattice iCEstick and iCE40-HX8K Breakout Board as unprivileged user
    cd /etc/udev/rules.d/
    sudo gedit 53-lattice-ftdi.rules
    [gedit opens, type next line]
    ACTION=="add", ATTR{idVendor}=="0403", ATTR{idProduct}=="6010", MODE:="666"
    [save and exit]
  18. Reload the udev rules
    sudo udevadm control --reload-rules
    sudo udevadm trigger
  19. Configuring the USB feedthrough from the host to the guest OS, both host and guest OS is Ubuntu ( original source: VirtualBox/USB )
    1. On the host OS:
      sudo adduser USERNAME vboxusers
      sudo apt install virtualbox-ext-pack
  20. Log out and log into your host OS for above changes to take effect
  21. Plug in your dev board, start the myhdl-virtual-machine and set the USB filter accordingly ( right click on the USB-symbol in the virtualbox status bar )
  22. Generate bitstreamfile of the hx8hboard example and load on the dev board
    cd ~/gitprojects/icestorm/examples/hx8kboard
    make all
    iceprog example.bin
  23. It took my nuc approx. 63 seconds to push the bitstream file to the dev board. ( Please let me know if you know a way to speed things up )

Getting the OLED debugging display working using only open source tools

A few days ago I tripped over a very cool project: Project IceStorm by Clifford Wolf. My previous workflow was only using open tools up to the point I had to convert the Verilog code into a bitstream file and push that to my Terasic DE0 Nano devboard. But now with project IceStorm I can model my design in python using myHDL, which results in a Verilog file. That Verilog file can now be converted into a bitstream file for the iCE40-FPGA(Lattice) using the tools in the IceStorm toolchain and then can be programmed into the configuration memory with icepack. If I now stop using Ubuntu, I could actually stop being evil (according to Stallman). :)

Anyhow, my next objective is to get the OLED debugging display running on the Lattice ICE40HX8K devboard.

The following clip shows a demo of the OLED debugging display running on the Terasic DE0 Nano devboard.

This display demo shows...

Read more »

  • 1 × Terasic DE0 Nano Devboard A Terasic Devboard with an Altera Cyclone 4, 32MB SDRAM, an 8 channel ADC and more.
  • 1 × Lattice iCEstick Evalutation kit A very cheap (approx 25 USD) devboard with a Lattice iCE40HX-1k, a PMOD-slot, some GPIOs and some LEDs. Thanks to the icestorm project it's possible to configure the FPGA using open source tools only.
  • 1 × Lattice iCE40-HX8K breakout board Like the iCEstick, but with more LUTs and much more accessible IOs.

  • The myHDL toolbox virtualbox image (and it's documentation) is good to go.

    Johannes K. Treu11/27/2016 at 12:59 0 comments

    The first version of the myHDL toolbox virtualbox image (3GB download from my google drive) is ready to use. This virtualbox image is 8GB when unzipped. I've tested this image on my Ubuntu 16.10 host by programming a Lattice HX8K board with the example that comes with the IceStorm project. Pushing that example bitstream file to the dev board took approx. 60 seconds on my machine - I'm pretty sure this can be way quicker, no idea how to improve the speed yet.

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seilerjacinda925 wrote 11/19/2019 at 15:48 point


Nice to meet you after viewing your profile i am Jacinda, from (jakarta) indonesia,

i have a project discussion with you please email me on: (

  Are you sure? yes | no

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