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Open Source ASICs Hack Chat

DIY ICs with Matt Venn

Wednesday, March 16, 2022 12:00 pm PDT Local time zone:
Hack Chat
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Matt Venn will host the Hack Chat on Wednesday, March 16 at noon Pacific.

Time zones got you down? Try our handy time zone converter. Reminder: this is the first Hack Chat this year after the time change in North America, so check carefully.

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When it comes to electronic designs, most of us are content to make (sometimes) useful circuits using chips that were designed by someone else. That's the beauty of this game, really -- a lot of the hard work has already been done for you in the form of microcontrollers, gates, memory, amps, and timers that are all well-characterized, cheap, and readily available. Well, maybe not that last one right now...

Supply chain issues notwithstanding, though, there's plenty to be said for designing your own silicon. It's not for everyone, of course, but if you need something custom, something that nobody else has ever dreamed up, then you really might want to consider rolling your own. Trouble is, most of us don't really have the tools to design something as exquisitely complicated as a silicon chip, and we don't exactly have access to a multi-billion dollar fab plant to spin up a couple when the whim strikes.

Or do we? As it turns out, we all do have access to the tools and technologies needed to turn our designs into silicon. We just need a little guidance, like that offered by Matt Venn and his "Zero to ASIC" course. You'll no doubt recall that Matt made appearances at both the 2020 and the 2021 Remoticons to talk about his efforts, and his recent partial success with his application-specific integrated circuit (ASIC). Now's your chance to ask Matt questions about the process, what the course is all about, and how you can make your silicon dreams come true.

  • Hack Chat Transcript, Part 2

    Dan Maloney03/16/2022 at 20:13 0 comments


    matt venn12:36 PM
    Thomas Parry did a livestream with me about his process

    https://www.zerotoasiccourse.com/post/livestream-with-thomas-parry/

    matt venn12:37 PM
    his day job is analog asic design, so he's good to see how a pro uses the open source tools

    Bruce D. Lightner12:41 PM
    Matt, Thank you for sharing. As you know, chip design is not easy---or everyone would be doing it! :-)

    Paul Stoffregen12:42 PM
    Any idea how many more shuttles are planned for the free open source stuff? I recall hearing 6 last year. Does #5 going in soon mean there will be only 1 more left?

    matt venn12:42 PM
    Hi Bruce, yes, it's not easy. Personally the long wait is a kller

    matt venn12:43 PM
    i remember improving so rapidly when the open source fpga tools came along and I could iterate on hardware a lot faster

    matt venn12:43 PM
    but mpw1 took a year so now I can learn from the mistakes I made then!

    matt venn12:43 PM
    Hi Paul! at least another 4 this year

    Paul Stoffregen12:44 PM
    oh, that's good to hear. I still sometimes fantasize about having time for this....

    matt venn12:45 PM
    yeah!

    matt venn12:45 PM
    it does take quite a bit of time

    Nick Kelsey12:47 PM
    does each die contain projects from multiple people + picorv32a?

    Paul Stoffregen12:48 PM
    Yup! I designed a chip 1993, which was made via Mosis. Spent all day and night on it for 3 months!

    matt venn12:48 PM
    wowza

    matt venn12:48 PM
    Nick, my applications generally combine lots of designs from different people,

    Paul Stoffregen12:49 PM

    Dan Maloney12:49 PM
    Curious about logistics. Do they just deliver a naked die? If so, how do you put it to work? Or do they do wire bonding and a lead frame, etc?

    matt venn12:49 PM
    but if you take a look at the submitted projects https://platform.efabless.com/projects/public you can see that most are just from a single person or group

    matt venn12:50 PM
    nice one Paul! I still haven't got my name on a die yet!

    matt venn12:50 PM
    Dan, no they ship WLCSP at 0.5mm pitch

    matt venn12:51 PM
    we got bare dies on mpw1 because they thought maybe it would help with the bringup

    if you don't know, we thought mpw1 was going to be a total write-off

    Tim Rudy12:51 PM
    How did it get "fixed", can you describe what happened?

    matt venn12:51 PM

    https://www.zerotoasiccourse.com/post/mpw1-bringup/

    ZERO TO ASIC COURSE

    MPW1 Bringup

    I submitted my first ASIC designs to the free Google shuttle in December of 2020. In October 2021, we heard there were serious clock related problems with the management area of the chip due to issues with the toolchain. It seemed unlikely that anyone would be able to get anything beyond a single blinking LED from MPW1.

    Read this on Zero to ASIC Course

    Tim Rudy12:51 PM
    Was it only one fab run?

    Patrick Van Oosterwijck12:53 PM
    I do wish they'd do more maker friendly packages. Like QFN at least

    matt venn12:54 PM
    yeah, not sure why they don't. I heard a few answers, one was price and the other was performance

    matt venn12:54 PM
    but tbh I didn't have too much problem with hot air

    matt venn12:55 PM
    and I think probably that's not a big barrier if you've got to the point of receiving your own chips. Also in the future they'll be delivering a few assembled pcbs along with the rest of the ics

    matt venn12:55 PM
    Tim, no we have had 4 now. 5th is on Monday

    matt venn12:55 PM
    another 4 this year

    Nick Kelsey12:55 PM
    what package is used?

    matt venn12:56 PM
    WLCSP

    matt venn12:56 PM

    https://www.zerotoasiccourse.com/terminology/wlcsp/

    ZERO TO ASIC COURSE

    WLCSP

    Wafer Level Chip Scale Packaging

    Read this on Zero to ASIC Course

    Nick Kelsey12:57 PM
    pin pitch?

    Thomas Capricelli joined  the room.12:57 PM

    Thomas Capricelli12:57 PM
    0.5 mm :)

    Nick Kelsey12:57 PM
    ouch

    matt venn12:59 PM
    yeah, it was my finest up to that point

    Nick Kelsey12:59 PM
    0.8mm = everyday PCB fab, 0.5mm is more specialized

    matt venn12:59 PM
    we weren't expecting great yield due to the hold timing issues, but I got similar results to Sylvain tnt munaut

    so I think my soldering was...

    Read more »

  • Hack Chat Transcript, Part 1

    Dan Maloney03/16/2022 at 20:12 0 comments

    matt venn11:56 AM

    matt venn11:56 AM
    good day!

    Dan Maloney11:56 AM
    Hi Matt! Welcome aboard!

    Nicolas Tremblay11:56 AM
    RPG map ?

    matt venn11:57 AM
    if you are 5nm tall, yes!

    James Ross11:57 AM
    This looks like his MPW1 layout

    matt venn11:57 AM
    yup

    Nicolas Tremblay11:58 AM
    It's the new zombie map in Call of Duty

    matt venn11:58 AM
    yeah it's got that ragged look

    matt venn11:58 AM
    this is with top metal removed, which isn't a perfect process

    matt venn11:58 AM
    otherwise it looks like this

    matt venn11:59 AM

    Nicolas Tremblay11:59 AM
    spreadsheet mode

    Dan Maloney12:00 PM
    Welcome one and all, let's get started! I'm Dan, I'll be modding today with Dusan as we welcome Matt Venn to the Hack Chat to talk about open-source ASICs and spinning up your own silicon.

    Hi Matt! I know you've been around HaD quite a bit, but care to tell us a bit more about yourself?

    Nick Kelsey joined  the room.12:00 PM

    Nicolas Tremblay12:00 PM
    Funny that they look so different

    matt venn12:00 PM
    hi everyone

    Ian Hanschen12:00 PM
    hi

    matt venn12:00 PM
    yes I've been doing electronics for a long time

    matt venn12:01 PM
    when I was a kid I bought maplin kits and assembled them, but didn't know how they worked

    I built a door lock that used some recycled 7 seg displays, and I hard wired them to spell 'open' when on, and nothing when off

    matt venn12:01 PM
    had no idea about how you would actually count numbers or change text!

    matt venn12:02 PM
    learnt slowly, got into microcontrollers, then fpgas

    matt venn12:02 PM
    got involved with yosyshq and the formal verification tools

    matt venn12:02 PM
    open source fpga toolchains

    matt venn12:02 PM
    i was at week of open source hardware (WOSH)

    when I saw Tim EDwards from Efabless showing a chip made with open source tools

    ilius123 joined  the room.12:02 PM

    matt venn12:03 PM
    so I downloaded them and tried them on an fpga design (the vga clock)

    matt venn12:03 PM
    I looked at running a course so I could tape-out, but the cost was about 10k,

    matt venn12:03 PM
    so I canned it. then 6 months later Tim Ansell announced the free shuttle program

    matt venn12:03 PM
    so I was in a good place and time to jump on and ride the wave

    matt venn12:04 PM
    now I have 4 tapeouts and preparing for my 5th

    matt venn12:04 PM
    160 people have taken my course and about 40 have taped out

    matt venn12:04 PM
    mpw5 tapes out on Monday, so I'm getting things ready for that at the moment

    Nick Kelsey12:05 PM
    what is the process size?

    matt venn12:05 PM
    130nm, which is a kind of hybrid I think. The gate width of the standard cell library are 150nm

    Nick Kelsey12:06 PM
    that would be ~1.2V?

    matt venn12:06 PM

    matt venn12:06 PM
    1.8v core

    tom12:06 PM
    Can you talk about what sort of FPGA designs can be easily ported? And what's harder coming from an FPGA?

    matt venn12:07 PM
    the easiest is pure digital with no hard ip blocks like multiplies or brams

    matt venn12:07 PM
    you can synthesise small memories with yosys out of flip flops but they are big and don't scale well

    we have openram for some hard sram blocks, 1kb in size

    tom12:08 PM
    And what if we wanted to multiply - just let it synthesize it?

    matt venn12:08 PM
    you could easly build a multiplier as well, for a dsp block but it would probably be quite big and not as efficient as one you'd get on an ecp5 for example

    matt venn12:08 PM
    yeah

    matt venn12:08 PM
    try not to divide!

    tom12:08 PM
    Right, that's true on FPGAs too

    tom12:09 PM
    Can you give an idea of what sort of timing / frequency can be had?

    James Ross12:09 PM
    The MPW has 16 slots of 300x300 um areas. Have any of the 160 been too constrained by this for their circuit design?

    matt venn12:09 PM
    so you can do ghz no probs

    matt venn12:10 PM
    but we have limited bw on the ios, they are quite old and only really go up to 50mhz

    Nick Kelsey12:10 PM
    300um x 300um or 800um x 800um max size - roughly how many pads and how many gates is realistic?

    matt venn12:10 PM
    there is an 'analog' version of the submission process that gives you 11 pads...

    Read more »

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