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Clock system is ready

A project log for BrainfuckPC Relay Computer

Von-Neumann 16-bit relay computer with Brainfuck++ instruction set

Artem KashkanovArtem Kashkanov 01/18/2019 at 08:140 Comments

I wire-wrapped clock system! the idea is to do instruction fetching stage and execution stage in one clock cycle. So we need to run impulse sequencer two times, on every clock signal edge.

I used simple schema with XOR element and D-trigger to do this and now everything works fine.

On high-speed camera you can see, how impulse sequencer signal wave is going.  And this process happened two times per one clock period.

Is Lights of impulse sequencer are flashing only ~10 ms of half-period it's funny to see how camera doesn't detect it because of stroboscopic effect.

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