I have created an initial set of schematics for this sub-system, but have not yet started wiring it up.

Here are design notes that help understand the schematics.

**Central Registers:** The Central Registers module implement the A, L, Q and Z registers along with implementing the ANDing, ORing and XORing of the A register with the Channel bus. The four central registers have numerous sources of data and various control pulses that perform specific functions. This is all straight forward logic.

The Z register has logic to perform the Z15 and Z16 command pulses. These pulses set the Z register to 040000 and 0100000 respectively.

The WALS command pulse is not simplistic.

Part of the central registers is the logic read from and write to the channel bus. This logic involves ANDing, ORing and XORing the contents of the A register with the bus data. To simplify the design and the chip count, four 74LS181 ALU chips are used. These chips have a 4-bit mode select. The Mode Control is set high to inhibit internal carries. The A data is set to the contents of the A register while the B data is set to the contents of the channel bus. The write to the channel bus is either a straight pass through, A anded with the channel data or A ored with the channel data. The read from the channel bus also can perform an xor of the data. Note that the instruction indicators are logic low. The following table defines the operations and the mode control values.

Function | S0 | S1 | S2 | S3 |
---|---|---|---|---|

WRITE | L | H | L | H |

WAND | H | H | L | H |

WOR | L | H | H | H |

READ | L | H | L | H |

RAND | H | H | L | H |

ROR | L | H | H | H |

RXOR | L | H | H | L |

WS0 = !WAND

WS2 = !WOR

WS1 = WS3 = High

RS0 = !RAND

RS1 = High

RS2 = !ROR + !RXOR

RS3 = !READ + !RAND + !ROR

**Arithmetic Logic Unit:** This module is the most complex of the modules requiring the most design effort. The X, Y, U and B registers are implement in this module. There is also a pseudo C register which is simply the 1's compliment of the B register. The X and Y registers have numerous control pulses to load them with various values. The X and Y registers feed four 4-bit adder chips used to add their values. The output of the adders is contained in the U register.

The U register's bit 16 is either the output of the ALUs or the sign bit (bit 15) extended into bit 16 if RUS is asserted.

The end-around carry bit logic is rather complex as the multiply uses 2's compliment arithmetic where everything else in the computer uses 1's compliment arithmetic. The sub-sequences can disable the end-around carry. The end-around carry is disabled during a multiply using the NEACON and NEACOF. This value is stored in a 1-bit register.

The X register has five control pulses that generate six outputs. These include B15X which generates an octal 060000, PONEX which generates an octal 000001, PTWOX which generates an octal 000002, a combination of PONEX and PTWOX which generates an octal 000003, MONEX which generates an octal 177776 and ZERO which zeros the X register. A bit table in MSB first format is as follows.

Pulses | Bit Pattern |
---|---|

B15X | 0100000000000000 |

PONEX | 0000000000000001 |

PTWOX | 0000000000000010 |

P1X + P2X | 0000000000000011 |

MONEX | 1111111111111110 |

ZERO | 0000000000000000 |

The only bits with any complexity are bits 1 and 2. Their equations are as follows.

1 = !M1X + (P1X + P1X P2X)

2 = M1X + (P2X + P1X P2X)

The U and B registers feed four 4-bit ALU chips that can perform a number of combinational logic sequences. The output of the ALU chips go directly to the Write Bus. The pulses that drive the ALU logic include the RB, RC and RU. The following equations are required and numbered for reference. WB is the Write Bus.

if RC then if RA then WB = A + B (A in WB) : 0 else WB = B : 1 if RB then WB = B : 2 if RU then if RC then WB = B + U : 3 else if RB then WB = B + U : 4 else WB = U : 5

Equation 0 is implemented separately due to the fact that the A value is contained within the Write Bus. The ALU chip has four control bits. The following table identifies the control bits required to implement the equations.

Equation | S3 | S2 | S1 | S0 | Function |
---|---|---|---|---|---|

1 | 0 | 1 | 0 | 1 | !B = C |

2 | 1 | 0 | 1 | 0 | B |

3 | 0 | 0 | 1 | 0 | !B + U |

4 | 0 | 0 | 0 | 1 | B + U |

5 | 1 | 1 | 1 | 1 | U |

This can all be translated into a truth table used to define the values of the four ALU control bits. The S0-3 values are defined as a hex value.

RB | RC | RU | S0-3 |
---|---|---|---|

0 | 1 | 0 | 5 |

1 | 0 | 0 | A |

0 | 1 | 1 | 2 |

1 | 0 | 1 | 1 |

0 | 0 | 1 | F |

Using Karnaugh maps, the following equations were generated.

0 = (B !C) + (A !B C)

1 = (A !C) + (!A B C)

2 = (A !B C) + (A B !C)

3 = (!A B C) + (A B !C)

There are three sequence portions that are duplicates and only need to be implemented once. These sequences are (A !B C), (!A B C) and (A B !C).

As if that weren't enough, the ALU implements six control pulses that ORes fixed values on the write bus. These are R1C, R15, R6, RB1, RB2 and RSTRT. The following table shows the values that are associated with each pulse.

Pulse | Octal | Bits |
---|---|---|

RB1 | 000001 | 0000000000000001 |

RB2 | 000002 | 0000000000000010 |

R6 | 000006 | 0000000000000110 |

R15 | 000015 | 0000000000001101 |

R1C | 177776 | 1111111111111110 |

RSTRT | 004000 | 0000100000000000 |

Most of the bits are either 0 or 1 if R1C is asserted. The exceptions are bit 12 which is also 1 if RSTRT is asserted along with bits 1, 2, 3 and 4.

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