At the beginning the antenna will be directly connected to the AD9226 Analog to digital converter, sampling at 65MHz. The 65MHz clock is generated by the FPGA, so that it can sample it well (more on this later)
Low pass (anti aliasing) 30 MHz filter: maybe later
10/20dB RF amplifier to use the whole 1 volt A/D input range
ANALOG TO DIGITAL CONVERTER - AD9226
The board has no clock reference (see the AD9226 board schematic) and therefore the 65MHz clock must be supplied by the FPGA. In this way:
- the AD9226 outputs data on the dropping edge of the clock.
- the FPGA samples on the clock rising edge
See the picture below and for further details see the AD9226 datasheet from Analog Devices.
A concern is about the clock jitter coming from the FPGA. Will it add noise to the received signal?
in this project ADC to DMA to Ethernet with a ZYNQ 7000, the sampling clock is generated outside the FPGA
The functions operating in the FPGA will be the followings.
- It will supply a 65MHz clock to the AD9226 and receive 12 bit data from it.
- 5 indipendent Digital Down Converters with selectable bandwidth (30 MHz, 10 MHz, 3 MHz, 1 MHz, 300KHz, 100 KHz, 30 KHz, 10 KHz) to show the spectrum image of up to 5 frequency ranges.
- 5 Digital Down Converters to tune up to 5 desired frequencies and decode them. e.g. the 5 FT8 frequencies on 80 40 20 15 and 10 meters
- The outputs of the 10 DDC will be sent to the Processor System (the CPU) inside the Zynq FPGA using and AXI DMA component. For an introduction to this technique see Using AXI DMA in Vivado
- I'd like to imitate such a structure ADC to DMA to Ethernet with a ZYNQ 7000
- I found a way to write/read read Zynq7000 PL (Programmable Logic) registers in the FPGA from the PS (CPU) FPGA itself. PS PL memory mapped intercom
The EBAZ4205 board and getting started with it
FIRST TEST ASSEMBLY
I built this first assembly to test the logic components by Xilinx Vivado.
The shield around the ADC tries to limit EMI from the Zynq.
The empt shielded area will contain a power filter to attenuate the electric noise eventually carried by +5V to the analog side of the ADC
The 16 wires flat cable ADC <-> FPGA (PL) connection carries:
ADC to PL
- 12 bits data
- Out of The Range (OTR) signal
PL to ADC
- sampling clock (65 MHz)
The Ethernet port is connected to the local LAN, obtaining an IP address.
In this way a user can view the waterfalls and tune the HF radio stations connecting by a browser to a http://192.168.1.xxx web site generated by a web server on the FPGA (PS)
It will run inside the Zynq PS to decode FT8 or other digital mode