Guido
Overview
At the beginning the antenna is directly connected to the AD9226 Analog to digital converter, sampling at 64MHz. The 64MHz clock is generated by the FPGA, so that it can sample it well (more on this later)
TODO:
Low pass (anti aliasing) 30 MHz filter. It will be useful to avoid interferences from FM radios
Block Diagram
The Zynq block are pretty consolidated while the Windows 10 PC is anything like an hypothesis.
Numbers
All the number crunching in the fabric logic is perfomed with two's complement.
When I write xx(yy), e.g. 32(28), I mean that the numbers are 32 bit two's complement but the maximum expected value is
- 2^28 <= value <= 2^28-1
ADC - Analog to Digital Converter - AD9226
The board has no clock reference (see the AD9226 board schematic) and therefore the 64MHz clock must be supplied by the FPGA. In this way:
- the AD9226 outputs data on the dropping edge of the clock.
- the FPGA samples on the clock rising edge
See the picture below and for further details see the AD9226 datasheet from Analog Devices.
A concern is about the clock jitter coming from the FPGA. Will it add noise to the received signal?
For example, in this project ADC to DMA to Ethernet with a ZYNQ 7000, the sampling clock is generated outside the FPGA
FPGA
The functions operating in the FPGA are the following.
- It supplies a 64MHz clock to the AD9226 and receive 12 bit data + 1 bit "Over The Range" from it.
- An internal signal generator 0.1 30 MHz AM modulated at 1KHz can be be used for testing purposes.
- One "capture block" will capture 16384 samples (at 64MHz) at a time. These samples are sent to the FPGA PS and from there to the SpectrumPy (a Python App running on a Windows PC) to show the full 32 MHz radio spectrum and waterfall.
- One or more DDC (Digital Down Converters) with selectable bandwidth (10 MHz, 3 MHz, 1 MHz, 300KHz, 100 KHz, 30 KHz, 10 KHz,) will zoom the radio spectrum and waterfall with increased resolution. (TODO)
- At lower bandwidths (100KHz, 30KHz, 10KHz and 3KHz) the DDC can be tuned on a specific frequency to demodulate and decode e.g. the FT8 frequencies on 80 40 20 15 and 10 meters.
Getting started with the EBAZ4205 board
This project is quite challenging, especially for those people who have never worked with Xilinx Zynq developement environment (Vivado, Vitis, Petalinux). Therefore I strongly suggest to start with a getting started project. See my Hackaday project: EBAZ4205 development environment
Show the full 0-32 MHz spectrum and waterfall
I built this first assembly and wrote some software to test this Hardware.
The shield around the ADC tries to limit EMI from the Zynq.
The empty shielded area will contain:
- a power filter to attenuate the electric noise eventually carried by +5V to the analog side of the ADC
and / or
- a 30 MHz low pass filter
The 16 wires flat cable ADC <-> FPGA (PL) connection carries:
ADC to PL
- 12 bits data
- Out of The Range (OTR) signal
PL to ADC
- sampling clock (64 MHz)
The Analog Input
I didn't like that AD9226 12-BIT 65MSPS board attenuates the input signal by -8,4 dB. So I decided to modify it to get some amplification, using far more 12 bits ADC range.
I designed a circuit like this:
obtaining some 16,5 dB gain compared with -8,4 dB of the original circuit that was this one:
The modified board:
The Analog Input Dynamic Range
With the first stage amplification I set, the maximum input signal (the one generating 2 Vpp between VINA and VINB) is around -6 dBm.
GUI
The Ethernet port is connected to the local LAN, obtaining an IP address.
In this way a user can view the spectrum and waterfall connecting via a TCP socket.
To do this,...
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NotBlackMagic
Alberto Garlassi
Dan Kisling
SingularitySurfer
EBAZ4205_SDR is always 0404 Sorry..