To keep the "right" digital level at every stage of the SDR looks quite challenging to me. 

"Right" means:

• enough high to reduce numerical noise
• enough low not to saturate the two's complement fixed point numbers

To test and simulate such a level in any stage (complex multiplier, CIC, FIR etc.)  I designed the test generator so that it outputs the maximum peak to peak signal level, which at 12 bits is between -2048 and 2047. This is the same maximum signal level the ADC can handle before saturating. 

Then I designed every following stage to output the maximum output level given the maximum input level. For example, see the complex multiplier.