A project log for Jelly

A minimal DIY 8-bit CPU made with TTL chips, to perform native brainfu*k language, extended to use three sequential access tapes.

Alvaro BarcellosAlvaro Barcellos 08/13/2022 at 23:120 Comments

Jelly have a pipeline of 16 cycles, to coordenate by enable or disable the tape controlers, and define actions as, move forward or backward, perform  read or write, also command increase or decrease tape bytes. All that is made by control signals, then microcode is a state of signals.

For easy Jelly have one signal for each control and all microcode, the states of signals, are stored into eeproms.

More changes and ideas.  

A weekend immersed into logs and projects of homebrew computers and TTL systems from Hackaday and Facebook groups of Minimalist Computers, does evolution in projects, learning is the best pill.