signals layouts

A project log for Jelly

A minimal DIY 8-bit CPU made with TTL chips, to perform native brainfu*k language, extended to use three sequential access tapes.

Alvaro BarcellosAlvaro Barcellos 08/13/2022 at 23:380 Comments

Jelly now have two buses:

external/internal bus

       block bus      (BOB, ONE, TWO, HLT, RD, WR, BK, FW)

       data bus        (D0, D1, D2, D3, D4, D5, D6, D7)

       extra bus       (VCC, GND, CLK, HLT, R0, R1, R2, R4)

only internal bus

      code bus       (M0, M1, M2, M3, M4, M5, M6, M7) 

      block code    (CP0, OE0, CP1, OE1, M8, M9, M10, M11)

      block data    (CP2, OE2, CP3, OE3, OP0, OP1, OP2, OP3)


D0-D7 are data bits, M0-M11 are eeprom address bits,

HLT main halt, CLK main clock, GND ground and VCC power,

OP0, OP1, OP2, OP3  select math operation

R0, R1, R2, R3  reserved for future use