Alvaro Barcellos
jelly-six.diglast update, halt circuit included- 122.33 kB - 02/03/2023 at 13:34 |
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jelly-six-tape.diggeneric pseudo tapedig - 26.75 kB - 02/03/2023 at 13:19 |
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jelly-six-halt.digadded halt statedig - 739.34 kB - 02/03/2023 at 11:40 |
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jelly-two-halt.pngcontrol logic steps for halt and flag signalsPortable Network Graphics (PNG) - 155.63 kB - 09/12/2022 at 14:24 |
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jelly-two.digfull bare bones circuit for Jellydig - 91.02 kB - 09/12/2022 at 14:24 |
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jelly-two-halt.digcontrol logic steps for halt and flag signalsdig - 33.39 kB - 09/12/2022 at 14:24 |
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jelly-two-loop.digtoggle logic for loops [ and ] using bob-one-rd-wr-zero signals to instant change eeprom pagedig - 9.26 kB - 08/30/2022 at 15:08 |
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Jellys-control.jpgbare bones schema for Jelly control moduleJPEG Image - 43.95 kB - 08/29/2022 at 20:20 |
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Jellys-lookup.jpgbare bones schema for Jelly lookup mathJPEG Image - 34.09 kB - 08/29/2022 at 20:20 |
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Jelly
A minimal DIY 8-bit CPU made with TTL chips, to perform native brainfu*k language, extended to use three sequential access tapes.