Here's the idea for the VGA interface: all five signals are derived from an 8-bit value that gets read out of a big SRAM framebuffer at 25.175 MHz:

D6 and D7 provide the horizontal and vertical sync signals, which are at TTL levels. I suspect that they're on 75-ohm cables like R, G, and B, so 62-ohm series terminations combined with the approximately 12-ohm output impedance of a 74AC gate will absorb any reflections. The vertical sync output will also be used to reset the 74HC393 address counters at the end-of-frame, since the frame data (420,000 bytes) doesn't fit evenly into a 512k x 8 SRAM - more details to come!

R/2R DACs

Each "DAC" block in the diagram above is just a 2-bit R/2R ladder with an additional resistor for 75-ohm matching and level conversion. Just the DAC part looks like this:

The output takes on four levels - with a DAC like this on each of the R, G, and B lines, we can display 64 colors. The maximum output of the DAC is 5 * 3/4 = 3.75V, and the output impedance is equal to R1. The VGA signal requires a maximum signal level of 1.4V (unloaded, it gets reduced to 0.7V by the 75-ohm parallel termination inside the monitor) and an output impedance of 75-ohms. Like @danjovic, we can use a little math to figure out the correct resistor network. A single resistor across the output of the R/2R string can set the output impedance and level:

We can set up simultaneous equations for R1 and R2 based on these two constraints. I don't have time for algebra these days - I have a computer for it. A little maxima, and we have the solution:

Hey, these are really close to standard 120 and 200-ohm values! Accounting for the small output impedance of the 74AC driver, a 390-ohm resistor works for the upper 2R's. The lower 2R should be 400, but 390 is close enough - it will keep the signal from saturating above 0.7V.

Even though the computer did it, I decided to check the math - a quick LTspice simulation verified the output impedance and signal level.