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Testing of the actual ASIC

A project log for Zinnia (MCPU5)

8 Bit CPU implemented in 100x100µm² IC area for TinyTapeout

timTim • 02/21/2024 at 21:34•0 Comments

I finally received the TinyTapeout board with the Zinnia+ MCU design!


I decided to use an RP2040 the exercise the I/O of the design. Since the code memory is external to the MCU, it needs to be emulated by a program on the RP2040.

Here is the output of the prime number generation program:
ExampleMore documentation and code here: https://github.com/cpldcpu/tt02-mcpu5plus/tree/main/validation
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Improved Instruction Set Architecture: Zinnia+

09/07/2022 at 19:56 • 0 comments

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