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Testbench and Assembler

A project log for Zinnia (MCPU5)

8 Bit CPU implemented in 100x100µm² IC area for TinyTapeout

timTim 09/07/2022 at 16:340 Comments

You can find the cleaned up designfiles including testbench and assembler on Github.

I ported two program examples from my other processor designs: Fibonacci number calculation and a prime number search algorithm.

Fibonacci examples seem to be quite commonplace for minimal processor implementations. However, Fibonacci can be implemented on a machine without any decision making (branching). So, proving that an architecture is able to execute Fibonacci is possibly not a proof of Turing completeness. This is why I prefer the prime number search.

The Fibonacci implementation is straightforward and shown below:

.=0
init:
    LDI  0
    STA  R0  ; a = 0
    LDI  1
    STA  R1  ; b = 1
loop:
    LDA  R1
    STA  R2  ; temp = b
    
    ADD  R0
    STA  R1  ; b' = a + b

    LDA  R2
    STA  R0  ; a = b

    OUT      ; display b

    BCC loop
idle:
    BCC idle

The testbench will show the output of the executed programs directly in the shell. In addition, a VCD file with waveforms is generated, which can be viewed with GTKWAVE or the WaveTrace plugin in VSCode.

grafik

The number in brackets shows the number of executed program cycles, the output shows the content of the accumulator when the "OUT" instruction in the machine code is executed.

grafikPrime number sieve:

;    divisor=2;    
;    while (divisor<number)
;    {
;        test=-number;
;        while (test<0) test+=divisor;
;        if (test==0) return 0;
;        divisor+=1;
;    }
;    return 1;


number     = R0
divisor    = R1
allone     = R7

.=0
start:
    LDI -1
    STA allone

    LDI 2
    STA number

    OUT                 ; first prime is 2

outerloop:
    LDI 2
    STA divisor            ;divisor = 2

    LDI 1
    ADD number
    STA number
loop:
    LDA number          ; test=-number;
    NEG
innerloop:
    ADD    divisor            ; while (test<0) test+=divisor;
    BCCL innerloop

    ADD    allone           ; if (test==0) return 0;
    BCCL outerloop       ; No prime

    LDI 1               ; divisor+=1;
    ADD    divisor
    STA    divisor

    NEG                 ; while (divisor<number)
    ADD number
    BCCL loop

prime:
    LDA number          ; Display prime number
    OUT

    JMP outerloop

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