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Structural sketches

A project log for YGREC16 - YG's 16bits Relay Electric Computer

Fork of #AMBAP, here I discuss about the physical implementation of the bitslice architecture with russian РЭС15 (see what I did here?)

Yann Guidon / YGDESYann Guidon / YGDES 04/02/2017 at 07:130 Comments

For the "computational unit", I have designed this structure:

The spacing between boards is approx. 1 inch so 18 boards will make a 18 inches wide boards ! (round that to 20 inches for the extra space). It is possible to reduce this to about 10 or 12 inches by using both sides of the main backplane :

The bitslice boards are about 10cm tall and plug into the backplane with dual-row, 90° 0.1" pin headers.

Each bitslice has separate blocks : register set, ALU, memory. They are interconnected on the backplane to enable or modify certain functions:

The memory is designed for 256 and 512 words. The "512" version is just an add-on and the bitplanes can receive one or two modules with 256 bits (and 16 relays) each.

The I/O is another story though.

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