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Architecture update

A project log for YGREC16 - YG's 16bits Relay Electric Computer

Fork of #AMBAP, here I discuss about the physical implementation of the bitslice architecture with russian РЭС15 (see what I did here?)

Yann Guidon / YGDESYann Guidon / YGDES 04/02/2017 at 21:090 Comments

A lot of progress was made in the last days ! In particular, the balanced tree system has been totally revamped in the log More balanced trees !

The "big picture" gets clearer and looks better than before. The basis is simple : pairs of bitplanes, one on each side of the backplane, each pair has a fanin of 8 for each address bit of the MUX16.

There are 6 address buses on the backplane :

Still missing is the I/O system. By the way, what is this I/O thing and how is it implemented ?



About 500 relays are allocated to the I/O system. There is no parity so 16 boards are populated. When rounded up, this amounts to 512 relays/16=32 relays per bitslice, or 16 relays for the inputs and 16 relays for the outputs.

Inputs are easy ! It's just MUXes and 16 relays afford us 16 input words, which is more than enough (have you ever seen a microcontroller with 256 bits of inputs ?

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