A lot of progress was made in the last days ! In particular, the balanced tree system has been totally revamped in the log More balanced trees !

The "big picture" gets clearer and looks better than before. The basis is simple : pairs of bitplanes, one on each side of the backplane, each pair has a fanin of 8 for each address bit of the MUX16.

There are 6 address buses on the backplane :

• src/i : 3 bits
• src/sh : 3 bits
• dest : 3 bits
• DRAM/lines : 4 bits
• DRAM/col : 16 decoded bits (total : 256 words)
• DRAM/col aux : 16 decoded bits (for the 512 words version)

Still missing is the I/O system. By the way, what is this I/O thing and how is it implemented ?

About 500 relays are allocated to the I/O system. There is no parity so 16 boards are populated. When rounded up, this amounts to 512 relays/16=32 relays per bitslice, or 16 relays for the inputs and 16 relays for the outputs.

Inputs are easy ! It's just MUXes and 16 relays afford us 16 input words, which is more than enough (have you ever seen a microcontroller with 256 bits of inputs ?