The TMS9995 is an extremely quirky processor. 

The Communication Register Unit interface is arguably the weirdest feature. It is a serial I/O interface to peripheral chips.

Memory space is byte-addressable, but CRU space is bit-addressable. A desired device is accessed by placing its software base address in Register 12 and exercising the CRU commands.

The CRU bit-space is 32K bits, because the least-significant address bit is used to send a data bit to the peripheral. 
The bit address is incremented when transferring multiple bits to/from a device.

I can see this has some advantages; for an 8-bit output port you would only need 3 address signals and 1 data signal, four in total instead of 8 data bits. It also simplifies bit operations, as there is no need to AND/OR bytes to manipulate single bits. The reduction of signal pins explains how they can get a full UART into a DIP18 package. 

On the other hand, the disadvantages are that the scheme is unique to the TMS 9000 family. No other CPU uses it, so there is little demand for it. 

I would like to add some more conventional devices as memory-mapped I/O. This will require modifying the address decoder to have "holes" in memory space.