Well, sheesh. Apparently I only found *two* such uCs in all those years' scavengings? Can't be...

K'den...

Well, this one's apparently got a core that's an extension of the 6502.

https://en.m.wikipedia.org/wiki/Mitsubishi_740

This, as I recall (or deduce), came from a VCR.

I was pretty stoked finding out its mask-ROM could be bypassed... Had to write it on the board! 

(I coulda sworn I'd done similar on at least a couple other boards. Where'd they go?)

In a way, I guess, that makes this a 6502 in a weird package...

Finding out /that/ it could be bypassed wasn't as simple as looking at the pinout... I'll give you a hint, it's one of these pins.

...Some more hints...

...but, yahknow... that could be for external /RAM/... which wouldn't be uncommon for microcontrollers ala 8051 or ATmega8515...

BAM! "Microprocessor Mode"

Alls yahs gots tahs does is connect the pin called CNVSS (intuitively: "Connect-to-VSS"?) to VCC. Of Course!

So, now we've got a souped-up 6502 to install behind a switch-panel and LEDs.

I gotta say, though, I'm a bit jealous of "Memory Expanding Mode's" multiplexing of the Address/Data lines with GPIO... hmmm...

No wait! They thought of that, too!

So that's that. A 6502 with a slightly wonky pinout, and a few extra features, if you aren't interested in compatibility.

Update 3-23-23: And here's an actual 6502 for comparison (Wikipedia).

So, not being familiar with 6502's, bus/interface-wise it seems to be lacking:

RDY, S0, and NMI. Lacking DMA pins, RDY would be my first guess at how to essentially "halt" the CPU for e.g. single-stepping. Maybe those SRDY pins are relevant, though.  My second guess might be that the clock itself is steppable, but I gather, from the various CPUs I've explored, that single-stepping/halting the clock isn't always a possibility, especially depending on the "process" (NMOS, CMOS).

The Wikipedia article mentions that often 6502 designs included faster memories whose accesses by other devices were "hidden" from the CPU, interleaved with its clock. I used a similar method, albeit in reverse, long ago for attaching a slower 8051 to a fast framebuffer; interleaving random CPU accesses on i.e. the low clock pulse, when high clocks were constantly used for redrawing sequential pixels. So maybe that idea could open up other options: e.g. with a fast latch attached externally, maybe a "jump -1" instruction could be injected into the path between the CPU and firmware [ROM?] when the external RAM or IO devices need it to wait before accessing them. (DMA in progress, halt [at address X?], STOP toggle-switch, etc.) Only thing is how to know if it occurs in the middle of a multibyte instruction read... Something to ponder. Or just use an interrupt, where the input is like a DMA-Request input, and the Interrupt-handler toggles a pin that enables the aforementioned "jump -1" latch, double-dutying as a "DMA-Acknowledge" output... hmmm...

Something like this could be useful for other such processors, as well (8051?).

Part of where I'm going, here, is a vague idea of having a single "front-panel", and a single array of I/O/Memory devices, slowly built-up over time... a cabinet, backplane, front-panel, etc. that ALSO contains *numerous* such processors, with the ability to switch them in and out of the system, maybe even in realtime, via software. And, at a very low level, (as opposed to, say, attaching them all via SCSI or GPIB). So, there needs to be some way to block one CPU while another is working on the bus.

...

I thought it a bit interesting to see how this chip was ordered from Mitsubishi: