I'm continuing the development of this project. My plan includes several critical steps:

1. FPGA Development
2. New Board Design, focused on cost optimization.

Here's what has been completed so far:

1. The architecture has been designed, built around a 16/24-bit Wishbone bus running at 96 MHz.
2. The specification for all platform registers is complete, specifically the MMU registers for both Legacy and Native platforms.
3. The following units have been designed and tested: CPU, PPI, PSG, CRT, PIC, NMI Controller, DMA Controller, SDRAM Controller.
4. The following units have been designed but not yet tested: Graphics Accelerator, Sound Synthesizer.
5. The system interconnect is 50% complete.
6. Current testing is focused on the unit comprising the CPU plus the Native MMU and Legacy MMU.

The main outstanding tasks are:

1. CRT to SDRAM address generator, pixel color generator, color palette, Scan Doubler, and HDMI output have not been started.
2. Work on the MCU, which will handle PMI and Sound Post Effects, has not yet begun.

I am hopeful for a successful outcome. The immediate next steps are to finalize the system interconnect and complete the testing of the current units before moving on to the remaining design and integration tasks.