Status: Video subsystem development is in progress.

What's been completed:

• The core video system is built and integrated. It includes:
  • SDRAM controller for video memory.
  • Color palettes.
  • Pixel pipeline.
  • Video buffer, scanline table, and HDMI controller.
• Two Wishbone interconnects are implemented: one for the SDRAM controller and another for internal registers/VRAM access.
• All graphics modes and memory addressing modes have been verified and are functional.

Current known issues:

• There are minor visual artifacts that will be addressed in a future update.

What's next:

The next step is to connect the Wishbone infrastructure to the host computer. This same interface will also link the FPGA to the on-board PMI microcontroller.

We have already completed the full specification for the UART/SPI to Wishbone bridge, which you can find here:

SPI/UART Specification

This work is expected to take a few days. Once complete, we will be able to write Python tests to validate all video controller capabilities.

The image below demonstrates a 256-color mode. With 16KB of memory, this currently results in 80 horizontal pixels, but the mode is designed to support 320 pixels in the final implementation.