This diagram illustrates the architecture of a video subsystem built around a video controller.

Main Data and Control Path:

1. Slave Interface: The video controller features an 8-bit wide slave interface for configuration and control. It transmits 24-bit addresses and data and is connected to the video controller's internal arbiter.
2. Internal Video Controller Bus: From the internal arbiter, the data bus leads to two main blocks:
   • 6845 CRTC (Cathode Ray Tube Controller): A historical microcontroller for generating video timing signals.
   • Palette Registers: Manage color transformation.
3. Memory Access Arbiter: A second memory arbiter is connected to the video controller. Its purpose is to multiplex access to the video memory between:
   • The video controller itself.
   • The internal Wishbone bus.
   • Key Feature: The data bus width of this arbiter is 16 bits.
4. Video Buffer Access: The video controller's output from this arbiter goes to a 32-bit wide video buffer. Due to this width and support for burst mode, the entire video buffer can be filled in a single access.
5. Connection to RAM: The memory arbiter is also connected to an SDRAM controller, which supplies the data to be displayed.
6. Image Rendering Pipeline:
   • Data from the video buffer is fed into a pixel converter, which can handle different color formats: 1, 2, 4, and 8 bits per pixel (bpp).
   • The resulting pixel index is sent to the Color Palette (Color Look-Up Table, CLUT), where it is converted into a 12-bit color (likely 4 bits for each R, G, B channel).
   • The color data is stored in a scanline buffer with a capacity of 720 pixels, which corresponds to the width of a standard video mode (e.g., 576i/p or 480i/p).
7. Video Output: The output of the scanline buffer is connected to an HDMI controller for generating the final digital video signal.

Future Development Perspective: The diagram uses grey color to indicate the approximate future connection point for a graphics accelerator (e.g., for hardware-accelerated 2D graphics).