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Memory-mapped I/O

A project log for risk-vee

An as-small-as-possible RISC-V implementation in Logisim.

Nicky NickellNicky Nickell 12/29/2016 at 21:230 Comments

While we only have 37 instructions (a subset of the RV32I ISA) testing each one manually is too tedious. In a more sophisticated simulation we could automate the testing (reset the processor, run an instruction or two, and then verify for proper state), but Logisim provides no means for us to do this. This means we'll do it the dumb way: instead of verifying correctness we'll assume everything works properly, write additional programs, and fix errors as they pop up.

To give us something to play with I'll be mapping some things into memory. Addresses 0xFF000000 up will be reserved for I/O and decoded into 16 1MB ports. Logisim provides tty and keyboard components which will serve the same purpose as a UART would in a physical implementation. Additionally, every good computer needs front panel switches and blinky lights so one of the ports will hold 32 of each.

I have the "what" somewhat figured out. Now it is just a matter of finding the time to tinker with the circuit.

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