Most of the interesting bits of my assembler are finished. For under 500 lines of sparsely commented javascript it already has a good deal of functionality. Highlights include:

• 18 pseudoinstructions (chapter 21 in the 2.1 RISC-V spec)
• register aliases according to the standard calling convention
• data assembler directives (byte, half, word, string...)
• user defined symbolic constants

Pseudoinstructions

Currently implemented pseudoinstructions are:

• nop
• li (load immediate)
• mv (move)
• not
• neg
• seqz (set equal zero)
• snez (set not equal zero)
• sltz (set less than zero)
• sgtz (set greater than zero)
• beqz (branch if zero)
• bnez (branch not zero)
• blez (branch equal or less than zero)
• bgez (branch equal or greater than zero)
• bltz (branch less than zero)
• bgtz (branch greater than zero)
• j (unconditional jump)
• jr (jump register)
• ret (return)

Register Names

The RISC-V standard calling convention gives a name to each of the 32 GPRs. They are as follows (this is table 20.2 in the 2.1 spec document):

With the exception of the floating point registers (which risk-vee doesn't have), each name is predefined for you in RVeA. Implementing this was probably the single largest improvement I have made so far (although labels are really nice too).

Assembler Directives

RVeA supports a handful of assembler directives. They are:

• .byte
• .half
• .word
• .string (a string terminated by a null byte)
• .stringu (as above except unterminated)
• .constant (define a symbolic constant for use in your program)

If you want to tinker around with it you'll need to grab node.js and then get the assembler from the risk-vee repository. After that assembling things is just a matter of:

node assembler.js whatever.s > whatever.bin

Notice that you have to send the output to a file yourself. At the moment RVeA just spits the assembled code to stdout. Right now it can only generate logisim binary files, but in the future I'll add options for raw binary output and Fallout 4 compatible files.

Once you have your binary file, right click on the RAM object in logisim, click load image, select your file, and then enable ticks (ctrl-k).

At some point I'm sure I'll get a HiFive 1. Extending RVeA for compatibility would be the obvious next step at that time. The biggest issue is instruction alignment: in a "real" implementation of RISC-V every instruction has to be word-aligned. Due to how risk-vee accesses memory (serially, a byte at a time) I'm not currently enforcing that, but it should just be a matter of tying the bottom two bits of the PC to 0. Well, that plus some checks for alignment in the assembler.

If you get your hands on a HiFive before you see a post about it here it means that you have one before me. Feel free to send me a message if you'd like to play around with RVeA and I'll see what I can do.