FM tuner RDA7088 is capable of processing RDS information as well apart from I2C bus and I2S output support!

Compared to my I2S output FM tuner project, FM tuner, IR remote control and I2S DAC remains the same.  

PIC10F200  replaced by ESP-01 and display module is added(LCD or OLED).

In ESP-01 out of four possible GPIOs only three GPIOs are used.  GPIO1 still available for future use.

FM tuner, OLED or LCD and EEPROM IC(24C0X) shares the same I2C bus.  EEPROM  used to remember the last used channel frequency and volume settings.  The GPIO3 input is used for IR remote receiver input(RX) pin.

Both LCD(I2C bus compatible 4 pin type) and OLED(4 pin type) modules were used for testing.  

Since with ESP-01 we have enough memory, speed and processing power it is much easier to develop the software using Arduino IDE with readily available libraries.

We can use any FM tuner Arduino library supports RDA Microelectronics tuners.  We can easily adopt the OLED or LCD modules from available Arduino libraries.  We can easily adopt any available IR remote control Arduino library.

The Wi-Fi feature of ESP-01 is NOT used in the project.  We can enable the Wi-Fi feature of ESP-01 for remote access, monitoring and OTA firmware update. Same setup tested with ESP-12, ESP32 and working fine. Since currently we are using just three I/O port pins, decided to use ESP-01.

ESP-01 pin map

       GPI00 - SDA(FM tuner + OLED or LCD + EEPROM)

       GPIO2 - SCL(FM tuner + OLED or LCD + EEPROM)

       GPIO3 - Rx - IR receiver 

If we enable the I2S output of RDA7088 the following GPIO pins will be assigned to the I2S signals

       PIN# 01 - GPIO1 - WS

       PIN# 16 - GPIO2 - SD

       PIN# 15 - GPIO3 - SCK

Even if we enable the I2S, still we will be getting the analog output on LOUT & ROUT pins concurrently!

We are using 32.768kHz crystal for RCLK required for the  tuner. The RDA7088 tuner supports 12MHz, 13MHz, 19.2MHz, 24MHz, 26MHz & 38.4MHz external RCLK for operation.  If we have any of the above frequency readily available or any PLL capable of generating any of the above mentioned frequencies then we can eliminate the 32.768kHz crystal used to generate the RCLK. 

REGISTER 04H and 06H details of RDA7088

REG 0x04

/////////////REG:04//////////////////////WR//
  Wire.beginTransmission(0x11);
  Wire.write(0x04);
  Wire.write(0b10001000);
//         -[B#FEDCBA98]-  
//             ||||||||______(08)-AFCD AFC disable 0- afc work; 1- afc disabled
//             |||||||_______(09)-SOFTMUTE_EN If 1, softmute enable
//             ||||||________(10)-RDS_FIFO_CLR 1 = clear RDS FIFO //RDSR _MODE???
//             |||||_________(11)-DE De-emphasis 0 = 75 μs; 1 = 50 μs
//             ||||__________(12)-RDS_FIFO_EN 1 = RDS fifo mode enable.
//             |||___________(13)-RBDS 1 = RBDS mode enable 0 = RDS mode only
//             ||____________(14)-STCIEN 1 = IINT ENA : STCIEN = 1 will generate low pulse on GPIO2
//             |_____________(15)-RDSIEN 0 = Disable 1 = Enable Setting STCIEN = 1 will generate a low pulse on GPIO2
  Wire.write(0b01000000);     //  Wire.write(0b01000000);
//         -[B#76543210]-  
//             ||||||||_______(0)-GPIO1[1:0] 00 = High impedance 01 = Reserved
//             |||||||________(1)-GPIO1[1:0] 10 = Low 11 = High
//             ||||||_________(2)-GPIO2[1:0] 00 = High impedance 01 = Interrupt (INT)
//             |||||__________(3)-GPIO2[1:0] 10 = Low 11 = High
//             ||||___________(4)-GPIO3[1:0] 00 = High impedance 01 = Mono/Stereo indicator (ST)
//             |||____________(5)-GPIO3[1:0] 10 = Low 11 = High
//             ||_____________(6)-I2S_ENABLED 1-ENABLED : 0-DISABLED
//             |______________(7)-GPIO1_INT_EN???
  Wire.endTransmission(); // stop transmitting
/////////////REG:04//////////////////////END//

 REG 0x06

/////////////REG:06//////////////////////WR//
  Wire.beginTransmission(0x011);
  Wire.write(0x06);
  Wire.write(0b00000010);
//         -[B#FEDCBA98]-    
//             ||||||||
//             ||||||||______(08)- WS_I_EDGE 0- normal ws internally 1, inverte ws internally
//             |||||||_______(09)- DATA_SIGNED 0- unsigned 1- signed (16-bit audio data)
//             ||||||________(10)- SCLK_I_EDGE 0- normal sclk 1- inverte sclk internally
//             |||||_________(11)- SW_LR Ws relation to l/r channel 0- ws=0->r, ws=1->l: 1- ws=0->l, ws=1->r
//             ||||__________(12)- I2S_mode_select 0- master mode : 1- slave mode
//             |||___________(13)- OPEN_MODE[1:0]
//             ||____________(14)- OPEN_MODE[1:0]
//             |_____________(15)- RSVD
  Wire.write(0b10000000);
//         -[B#76543210]-    
//             ||||||||
//             ||||||||______(0)-R_DELY-R Channel data Delay 1T
//             |||||||_______(1)-L_DELY-L channel data Delay 1T
//             ||||||________(2)-SCLK_O_EDGE If 1, invert sclk output when as master.
//             |||||_________(3)-SW_O_EDGE If 1, invert ws output when as master.  
//             ||||__________(4)[4]-I2S_SW_CNT[4:0]
//             |||___________(5)[4]-I2S_SW_CNT[4:0]
//             ||____________(6)[4]-I2S_SW_CNT[4:0]
//             |_____________(7)[4]-I2S_SW_CNT[4:0]
//                           4'b1000: WS_STEP=48.000kbps;
//                           4'b0111: WS_STEP=44.100kbps;
//                           4'b0110: WS_STEP=32.000kbps;
//                           4'b0101: WS_STEP=24.000kbps;
//                           4'b0100: WS_STEP=22.050kbps;
//                           4'b0011: WS_STEP=16.000kbps;
//                           4'b0010: WS_STEP=12.000kbps;
//                           4'b0001: WS_STEP=11.025kbps;
//                           4'b0000: WS_STEP=08.000kbps;
   Wire.endTransmission();  // stop transmitting
/////////////REG:06//////////////////////END// 

The above two registers can be accessed using random or sequential. The above code uses random access.