To support this effort, I have prepared a concept computer circuit that I would like to share with you. The core component of the processor subsystem is a Zilog eZ80190 CPU with 2Mb Flash ROM and 6Mb RAM. The I/O will be a simple UART to USB converter. The ATmega128 will shadow the processor subsystem bus, giving it total control over the eZ80190 CPU, including clock cycle generation. Meanwhile, the softcore-debugging subsystem can be isolated from the bus processor subsystem and run at its full potential of 50MHz.
I have previous experience with softcore development for the 65C02 CPU and I am confident that we can successfully develop a softcore for the eZ80190 CPU. Thank you for your attention and please let me know if you have any questions or concerns.