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Isetta TTL computer

TTL Retro computer runs 6502 and Z80 code. Has video, sound and filesystem. Runs a Windows-like OS. No microprocessor or FPGA.

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This computer is built from simple TTL circuits. There is no microprocessor, microcontroller or FPGA. It can execute 6502 instructions and can on-the-fly switch to Z80 instructions and back.
The video has max. 640 x 400 pixel graphics with several colors. It also has on-board file system and sound generator. The prototype is working and runs ZX Spectrum games, 6502 BASIC, and the SymbOs operating system.

BREAKING NEWS

The Isetta computer can now run the SymbOs operating system ! On april 3rd, 2025 it ran the first SymbOs applications. SymbOs is a pre-emptive, multitasking operating system with graphical user interface, comparable to Windows 95. On Isetta it still has several small bugs, but these are solvable. SymbOs stores its applications and data on Isetta's micro-SD card. Many applications take only a second to load.

HOW DOES IT LOOK

SPECIFICATIONS

 CPU:
    - Runs Z80 and 6502 code
    - Speed 12.5 MHz (80 nS cycle time)
    - Memory 512 kByte RAM (with bankswitching)
    - programmable/upgradeable microcode (3 flash chips)   
    - 42 integrated TTL circuits. No microprocessor or FPGA.

 I/O:
    - video VGA 320 x 200 (64 colors), or 640 x 400 (16 colors)
    - keyboard and mouse (both PS/2)
    - sound generator (AY-3-8910 compatible)
    - real time clock
    - microcoded video processor, sound processor, I/O processor
    - 9 integrated TTL circuits for the I/O

 Storage:
    - 32 Mbyte on-board
    - micro-SD card (removeable)

 Connectivity:
    - File transfer to/from Raspberry Pi
    - WiFi on-board (future)

 Applications:
    - SymbOs operating system
    - Runs ZX Spectrum games
    - Runs several BASICs (Apple I, Altair, TRS80)

 Other:
    - pcb 119 x 150 mm  (4.7 x 5.9 inch), 4 layers.
    - powered by 5V USB

 Principles for the design:

 - No microprocessor, microcontroller, SOC, FPGA, CPLD, GAL, PAL or 74181
 - All components have good availability at the big distributors
 - Low number of components
 - No fine-pitch devices that are difficult to solder

SELLING KITS

Now, there is a KIT available, to build your own Isetta ! The first kit was successfully built by Vadim.

DISCUSSION

For questions or tips/remarks you can use the discussion section at the end of the main page.  Or you can send a PM, or join the discussion at the RetrocomputingForum / Isetta. BTW, where do you come from ?

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IDEA

The idea for this design was born at the end of januari (2023). 

The heart of a computer is the CPU. In most computers, the CPU is a single integrated circuit (a Microprocessor). But it is also possible to build your own CPU from parts that perform simple functions.

While many homebuilt CPU's have their own, unique instruction set, I decided that for this project the CPU would use an existing instruction set. Also, I wanted to build the CPU from parts of the TTL family. That are integrated circuits, that can perform elementary logic functions. They were first used in the 60's of the previous age. I use a modern version of these circuits, that use less power.

So which instruction set to use ? The CPU inside your laptop or cellphone is much, much too complex to build. But it is possible to use an older CPU from the time when microprocessors just became available. There were two processors that can be regarded as the Beetle and the Deux Cheveaux of the beginning of the homecomputer age.

Those processors are the MOS Technology 6502 and the Zilog Z80

The 6502 is famous because it was the heart of the Apple 1, the Apple ] [, the Commodore 64, the Nintendo NES and many others. The Z80 is well known because it was used in the TRS-80, the ZX Spectrum and the MSX computers, and it was widely used to run the CP/M Operating system, see also this Z80 introduction video.

So now, I had to decide whether to use the instruction set of the 6502 or that of the Z80. But then I thought... why not build a CPU that can do both ?

I did spend a few months searching for a good design that would give good performance...

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  • We have Sound !!

    roelh4 days ago 2 comments

    Finally, the PSG (Programmable Sound Generator AY-3-8910) is coming to life. It was harder than I thought. But it now has the 3 channels for tone or noise, with independent frequency and volume control. Only the the envelope generator is not present yet. The sound is generated by microcode, no actual AY-3-8910 is used, but the sound is controlled in the same way as on a real sound chip.

    It generates the typical sound of the eighties computer games.

    It can now provide sound for the SymbOs operating system !  And here you see the first Youtube video of Isetta running SymbOs (made by Prodatron):


    (The start-up screen of Isetta will have to be modified, it's quite a mess at the moment.)

    A new version of the Isetta programming manual is now in the file section. It includes the commands to control the sound generator.

    OPERATION

    There are four 1 kB sound buffers, one for each of the three channels, and a fourth one for noise.

    The squarewave sounds are generated in an unrolled loop. So if a wave has 5 samples 'high' and 5 samples 'low', to generate one period there will be two sequences that each put samples in the buffer, with each having five "(pc++) <- T" micro-instructions in a row. (Note the program counter is used as auto-incrementing pointer to the buffer).

    The value in T is the required amplitude for this sound (positive value for high samples, negative value for low samples). So there is no separate volume-control stage, like the real PSG has.

    At each scanline interrupt, a byte-sized sample is taken from each of the four buffers, the four samples are added and sent to the D/A converter (resistor array RN1). So the sample frequency is the same as the VGA line frequency, 31.25 kHz.

    To control this, there are two Z80-output ports. One to select a AY-3-8910 register, and another one to write a byte to that register. The Z80 output ports can also be used by the 6502 processor.

    EFFICIENCY

    For each channel, producing samples takes around 3 cycles per sample. (The unrolled loop produces 8 samples 
    on average, single cycle per sample, with also 16 cycles overhead).
    For a full 525-line frame, this is 1575 cycles per channel.
    Noise has it's own channel, so there are 4 channels, together taking 6300 cycles each frame.


    In each frame, 120 lines are for the CPU, minus interrupt it's around 350 useable cycles per line. Per frame,
    this is 120 * 350 = 42000 available cycles. So the sound takes 15% of the CPU time.
    For frequencies higher than 1kHz, there are just a few samples produced in each loop, so there is more overhead.

    LINKS

    There are several very nice articles about sound generation.

    Want to know everything about synthesizers:

    https://www.soundonsound.com/series/synth-secrets-sound-sound

    Building the AY-3-8910 fully from TTL chips:

    https://github.com/mengstr/Discrete-AY-3-8910

    Very good description of the AY-3-8910:

    https://www.cpcwiki.eu/index.php/PSG

    Article about Linear-feedback shift registers, used to generate noise:

    https://en.wikipedia.org/wiki/Linear-feedback_shift_register

    The Isetta noise generator comes from this article. It's a 16-bit Galois type, quite simple:

           unsigned msb = (int16_t) lfsr < 0;   /* Get MSB (i.e., the output bit). */
            lfsr <<= 1;                          /* Shift register */
            if (msb)                             /* If the output bit is 1, */
                lfsr ^= 0x002Du;                 /*  apply toggle mask. */
    
    

    Sound generation in the Novasaur TTL computer:

    https://hackaday.io/project/164212-novasaur-cpm-ttl-retrocomputer/log/184708-roll-your-own-sid-chip

    Interactive demo, shows harmonics of square waves and triangle waves:

    https://www.desmos.com/calculator/emfmoefwqu...

    Read more »

  • Do-It-Yourself KIT available

    roelh05/21/2025 at 17:45 0 comments

    KIT Available

    The first Isetta kit was successfully built by Vadim:

    In [this log] you can see all ins and outs of the kit. Of course, with the kit, you will receive the latest schematics and software versions.

    Just a few pcb's are available for the kit. A few modifications must be done (the wires that you see on the pictures), but these modifications are clearly described. I wil soon change the pcb design to accomodate the modifications (and do some other changes), but it will take a few weeks before I have those pcb's available.

    SymbOs

    Good progress was made on the SymbOs implementation. The most serious bugs are fixed now. Currently I am working on the microcode for a sound generator, that will work similar to the AY-3-8910, and that can also be controlled by SymbOs. 

  • Come and see Isetta running Symbos

    roelh04/27/2025 at 20:23 0 comments

    On may, 10th you can see Isetta running SymbOs !

    Isetta will be at the "MSX Vriendenclub Mariënberg", together with Prodatron (designer of SymbOs), and myself.

    https://raymondmsx.nl/home_mvm_eng.html   English
    https://m-v-m.lookpages.nl/home/  Dutch

    Place:
    Buurtgebouw de Grendel
    Wicher Hentostraat 17
    7692 AL Mariënberg

    Time: may, 10th 2025, from 10 a.m. till 4 p.m.

    As a first time visitor, the meeting is free. 

    It would be nice if you send me a reply or PM if you want to come.

  • Programming manual, microcode and Blitter

    roelh03/12/2025 at 12:10 0 comments

    PROGRAMMING MANUAL

    An Isetta Programming Manual was made, that describes all features that are available to the assembly program.
    You can find it in the File Section.

    It describes most of the I/O ports. 
    It also describes the video system, bankswitching, ports used for the Blitter, and describes a debugger that I made.

    MICROCODE INTRO

    One of my plans was, to have some microcode support for writing to the screen. 

    Writing to the screen, in Z80 (or 6502) assembly language, can be very tedious. The screen is pixel based. There are several complications:

      - in 640x400 mode, there are two pixels per byte
      - we might have graphics encoded as 2 bits per pixel (4 colors), this must be converted to 4 bits per pixel
      - We might have transparent pixels (for sprites). So sometimes, in a byte, one nibble must be written but the other stays the same.
      - the upper and lower half of the screen are in different memory banks
      - perhaps the 4-bit color pixels must be converted to another 4-bit color code

    A Z80 assembly program to do this will be difficult to write, especially because it should be quite fast (to get the screen written in an acceptable time).

    MICROCODE FEATURES

    To get a good performance, it would be better to write screen handling in microcode. On Isetta, programming in microcode has the following features:

      - A microcode instruction is 24 bits, and is totally different from a Z80 or 6502 instruction.
      - While the main purpose of the microcode is, to implement Z80 or 6502 instructions, it can also be used to do other functions.
      - A 24-bit micro-instruction can be fetched from microcode flash memory while a data byte is transferred to/from data memory (Harvard style). A micro-instruction always executes in a single cycle (80 nS).
      - The 24-bit instructions are addressed by the instruction register (8 bit), a step counter (4 bit), a page register (4 bit), and the flag F (1 bit).
      - The micro-instructions can read and write flags, and have conditional execution, that lets the F flag choose between two micro-instructions.
      - During execution of a Z80/6502 instruction, when the required steps are done, a micro-instruction will load the instruction register (IR) from an address that is in the program counter (PC++), reset the step counter to 0, and might set the page register to a new value.
      - If, at the end of the 16 steps, the instruction register (IR) is not loaded again, the IR will automatically increment, because the lower 4 bits of the instruction register is also a counter. So a sequence of micro-instructions can be 256 cycles long. If IR is still not loaded, it will go back to the first of these 256 steps. 
      - If the instruction register is loaded, it does not have to be loaded from the PC address. It can also be loaded with a constant (to jump to a fixed next instruction), or can be loaded from a register in memory. It is possible to write simple programs without using the program counter.

    MICROCODE DETAILS

    What do the micro-instructions do, more in detail ?

      1) Read the next 24-bit micro-instruction (pipelined), from one of two 'tracks' chosen by the F flag.
      2) Determine memory address and memory bank. Memory address can come from:
          - the data pointer (DPH/DPL), or
          - the program counter (PC) with optional auto-increment, or
          - a small fixed value (included in the 24-bit instruction). This is divided in two ranges (selected by microcode):
               - A) A fixed range of 64 bytes
               - B) A selection between two other ranges of 64 bytes. Selection is done by the output bit EXX. The BC, DE and HL registers of the Z80 are stored in this range.

         There is an option to set the lowest address bit to 1. This is useful to read the MSB of a word, without having to increment...

    Read more »

  • Announcing kits on the last day of 2024 !

    roelh12/31/2024 at 12:44 0 comments

    Both prototypes that I have built worked without any HW problem (of course there were SW problems now and then). On the first one, I ran The Great Escape (in its self-running mode) continuous for almost a week (and then I stopped it). This gives confidence.

    SELLING KITS

    I could now soon start with selling kits.  If you are interested, let me know in the comments or in a private message.

    [edit may 2025: Kits are available NOW. The first kit was successfully built by Vadim. ]

    The price of the kit will be around 100 Euro (USD 110) (Shipping costs not included). You will need to have some experience in building electronic kits.

    - You buy the bare pcb from me, for 30 Euro. I will make instructions and a detailed list of parts.
    - You buy all parts from an electronic parts supplier, like Mouser or Digikey. Cost around 65 Euro, free shipping at several suppliers.
    - You get the PDF of the actual schematic
    - An enclosure is not yet included. But the pcb is designed to fit in a Hammond RM2055S enclosure.

    Selling complete Isetta's might come later.

    What more do you need

    You need several other things, that you might have lying around:
    1. A universal programmer to program the three flash chips with microcode. Or the Isetta programmer pcb.
    2. A Raspberry Pi (RPi), for transferring files to the 32MB on-board storage of Isetta
    3. A 5 volt power supply with USB-B plug
    4. A monitor (CRT or LCD) with VGA connection, with cable and 15-pin connector
    5. A PS/2 keyboard
    6. A PS/2 mouse (not needed for all applications)
    7. A micro-SD memory card (might be needed by some applications)
    8. An adapter to connect the micro-SD card to your Windows/Linux/Mac computer
    9. A speaker with amplifier, with 3.5mm (stereo) plug. For sound.

    Programming the microcode

    You can use a regular, universal programmer to program the microcode in the three flash chips (PLCC44 case). (I have not done that myself yet, I use the RPi). But, it is very likely that new microcode versions will appear, so you have to use sockets on the pcb to be able to reprogram them. Sockets can be unreliable, however.

    You can also use the special Isetta programmer pcb (that I will sell you for 10 Euro). It needs 10 TTL chips, and connects the Isetta to the Raspberry Pi. The Raspberry Pi can now program the microcode flash chips while they are soldered on the board. The programmer pcb also allows the RPi to send files to the on-board storage, and allows low-level testing and single-stepping the Isetta. The low-level testing is VERY useful if you soldered your own Isetta.

    The RPi also needs a monitor (HDMI connection), USB keyboard, USB mouse, and power supply.

    Note that, as soon as the microcode is programmed and files are transferred, Isetta can work fully stand-alone without needing the RPi or the programmer pcb. In the future, Isetta should be able to fetch files from the micro-SD card, or through its WiFi connection. [edit: SymbOs uses the micro-SD card]

    If you only need file transfer, you can connect the RPi with 4 wires to Isetta, without needing the programmer pcb.

    Future plans

    - Make a good description of the available I/O instructions
    - Provide more microcode support for writing to the screen
    - Implement a nice sound generator
    - Support micro-SD card and WiFi
    - Have an editor/assembler on Isetta
    - Add applications
    - Have a nice operating system

    I could use help ! But you'll first need the hardware...

    What did I do since the last log ?

    - Write text to the new 640x400 screen
    - Implement the RST #38 interrupt (interrupt mode 1) at each video frame. Can be enabled/disabled with EI, DI instructions.
    - Made a mouse driver in microcode. An I/O instruction can now read messages from the mouse.
    - Completed several changes that were needed due to HW changes on the new pcb
    - Created an output instruction to do bankswitching

    END OF THE YEAR

    Best wishes for the new year ! That you and your loved ones all be happy and healthy !

  • New pcb, new video mode

    roelh11/17/2024 at 13:07 0 comments

    A few weeks ago I received the new pcb (ISA2442). Several things have changed with respect to the first pcb, so several software things had to change.

    One of the main changes was the 640 x 400 pixel mode. On the first pcb, a byte from memory represents 8 pixels, and the byte tells for each pixel if it has foreground color or background color (these colors being programmable).

    On this new pcb, a fetched byte has information for only two pixels (pixels last 40nS). So we can simply have 4 bits (16 colors) per pixel. The color of each of the 256000 pixels can be set independent from the others.

    Today I got this new mode to work. 
    On the picture you see mainly uninitialized memory, that gives a random, noisy pattern of colored pixels.
    In the first row I programmed the 8 basic colors, and the second row shows the same colors with low intensity. So the upper two rows show all 16 available colors in this mode.

    On the last row I made horizontal and vertical stripes, and a few checkerboard-patterns of two colors, that give the 
    impression of another color (orange, and variants of green and blue).

    You might ask why this is only 400 lines instead of the standard 480. This is because the processor can not run the user program during the active part of the video frame, because it is busy rendering the screen. By using only 400 lines, the processor has more time to run the user program.

    The 320 x 200 pixel mode (used for the ZX Spectrum screen) was essentially unchanged. 

  • Second PCB version ordered

    roelh10/19/2024 at 08:49 1 comment

    Yesterday I finally ordered the new PCB. This PCB is sponsored by the kind people of PCBWay, the well-known high-quality PCB fabrication company from China. During production you can always check in which production state your pcb is, and I watched an impressive series of videos that show all steps in the production process.

    This is the KiCad 3D-impression of the new PCB:

    With respect to the first PCB, the main changes are:

     - fix mistakes (VGA connector)
     - add Mouse connector
     - add HW for sending info to keyboard (and mouse)
     - add memory bank select
     - change video pixel/color generation for 640x400 mode
     - change WiFi module type
     - simple 4-wire connect to Raspberry Pi (for file transfer)
     - instead of a SPI header, a micro-SD card connector is mounted
     - changed SPI reading, it can now be done in 2 cycles/bit (instead of 5)

  • Changed bankswitching system

    roelh10/14/2024 at 12:59 0 comments

    In this previous log I described the new bankswitching system. But I wanted to add another mode (Linear mode). It would be nice if a program could access the whole 512kB memory without bankswitching. The address would be in a 3-byte register, with 19 significant address bits. A simple processor with 19-bit addresses could then be implemented.

    For programming the Z80 or 6502, it is not needed to know all this. You only need this if you implement a bankswitching system or a new processor microcode that accesses the whole memory. Probably it is only for myself.

    I came up with the following: (All images can be enlarged by clicking them)

    LINEAR MODE

    The functions are essentially the same as in the mentioned previous log, but I added the Linear mode. For program code, the upper bits A18 and A17 come from a bank select register, and A16 comes from microcode. For data, upper bits A18, A17 and A16 come from another bank select register. So, the upper three address bits can be different for program and data. Also new is, that this bank select register can be loaded from a memory-resident register in a single cycle.

    APPLICATION and KERNEL

    It is intended that, for Application and Kernel modes, BS_2 and PC18 are always written with the same value. That makes our table slightly less complex:

    This diagram shows all modes. The modes are controlled by signals in the microcode and the bank select registers, as shown.

    HARDWARE IMPLEMENTATION

    The result is a bit complex because I didn't want to add more chips. Another complication is, that the address must be available quite fast, so there can not be long propagation delays. The following diagrams (there are seven) explain all modes, and also the way it is implemented. The used colors are the same as in the table above.

    You find the bankswitching control registers at the top of the diagram. The microcode control signals are at the left side. At the right side, you find the five highest address bits, their value indicated by '0' or a color.

    REGISTER MODE

    This is the simplest. The (memory resident) registers are in the very first 256 bytes of memory. This mode is selected by CTL_M1 = 1. The CTL_M1 signal switches all upper address outputs OFF, so all upper address bits are zero. The register in question is selected by several bits in the microcode.

    The value in the bank select registers is irrelevant.

    TABLE / ZPAGE

    In this mode only the lower 8 bits of a data or code address are used. The other bits are zero, but A16 and A17 come from microcode. It is used for 6502 Z-page, for an identity table and a shift-right table. If A16=0 and A17=0, this mode can not be used (that is the domain of the memory-resident registers).

    This mode is selected by microcode signals only. The value in the bank select registers is irrelevant.

    NATIVE

    This is the main addressing mode of the first prototype. The upper address bits are 'hardwired' in the microcode. Bit A18 can no longer be used, that should not be a big problem because this will no longer be the main addressing mode.

    This mode is selected by microcode signals only. The value in the bank select registers is irrelevant.

    APPLICATION MODE

    Here, the upper three address bits are freely programmable in the bank select register U50. It is advisable to set BS_2 equal to PC18, otherwise the topmost address bit is different for code and data (also for the following two modes kernel slot1/slot3).

    This mode is selected by microcode signals in combination with APPL = 1. Yes, the APPL signal got it's name from this mode.

    KERNEL SLOT1

    The 64k addressing range is split up in four slots:

    • Slot 0 ( 0000 - 3FFF )
    • Slot 1  (4000 - 7FFF)
    • Slot 2 (8000 - BFFF)
    • Slot 3 (C000 - FFFF)

    In this kernel-slot1 mode, normally the microcode selects which 64k bank is selected (orange signals). But if the address is in slot 1, the bank number comes from the bank select register (light...

    Read more »

  • Fixing the LDIR instruction

    roelh09/17/2024 at 20:18 0 comments

    In the past weeks, I've been working on a new pcb design. That's now almost done.

    This weekend I looked at my TODO list, and I found, no surprise, the LDIR instruction.

    In one of the previous logs I mentioned that there was an error in the LDIR instruction. It didn't behave correctly when an interrupt occurred.

    What is the LDIR instruction ? 

    In the Z80 processor, this instruction can copy a whole section of memory in just a single instruction. It takes three 16-bit sized values as input:
     - A source address in register pair HL
     - A destination address in register pair DE
     - A byte count in register pair BC

    LDIR stands for Load, Increment, Repeat.


    It will do the following actions:
     - read a byte from the address at location HL
     - write that byte at location DE
     - increment the addresses in HL and DE
     - decrement the byte counter in BC
     - if the byte counter is not zero, repeat the actions
     - if an interrupt occurs during this instruction, it will be handled and the actions will continue after interrupt is handled.

    LDIR has a 2-byte opcode: ED B0

    Optimizing the LDIR

    The LDIR was already optimized, with 10 cycles per copied byte, but I had the strong feeling that something better was possible. I didn't try to find the problem in the old version, just started again from scratch.

    Isetta has only a single hardware data pointer. But nothing keeps us from using the program counter as a data pointer ! For a normal instruction, that would cost way too many cycles, but for a repeated transfer instruction this will pay off. The LDIR microcode should just save the PC to a temporary location, and copy the HL register pair into the PC. Now the PC can be used to get the bytes out of memory. When all actions are completed, the PC is copied back to HL, and PC is restored from the temporary location. The existing, broken LDIR version also had this feature.
    And as a bonus, the PC register can increment in the same cycle where it addresses a byte to be fetched.

    The destination pointer (register pair D E) is copied to the hardware registers DPH and DPL. The byte, fetched with the address in PC, can now be stored at the address in DPH/DPL. There is a microinstruction that increments DPL, it can also detect a carry, but there is no possibility to increment the DPH register, because it can not be accessed after the change that is described HERE. But we could increment the D register and re-write DPH with the result. This will at least take 3 more cycles (microinstructions).

    Then we must decrement the count in the BC registers. So first decrement C (2 cycles) and, when it drops below zero, decrement B (also 2 cycles). 

    The problems are in the counting, and in the increment of the upper byte (DPH), 

    But if we unroll the loop, in sections of 8 transfers, we don't have to count each byte. We simply subtract 8 from the LSB of the count, at the beginning of the unrolled loop. But when the count is lower than 8, we jump to a slow old-fashioned loop. This will decrement the MSB of the count when that is needed, and then go back to the unrolled loop. The slow loop will also check for zero to determine if the instruction has completed.

    It would be nice if we never had to increment the upper byte (DPH)...  What if we never increment the upper byte in the unrolled loop ? Before the unrolled loop starts, we could check if the lower byte (DPL) would overflow in that loop. That would happen if that lower byte is higher than 0xF7 (247), and in that case we do the old-fashioned loop, and when the upper byte has been incremented, we go to the unrolled loop again.

    Now, the sections of the unrolled loop have only 3 cycles:
     - A <- (PC++)
     - (DPH/DPL) <- A
     - inc DPL

    Pseudo code of the fast copy loop:
     - if LSB of the count < 8, goto slow loop
     - if LSB of destination > 247, goto slow loop
     - count = count - 8
     - copy the DE registers (destination)...

    Read more »

  • Progress of new PCB

    roelh09/07/2024 at 10:14 0 comments

    Here is an impression of the new PCB (Image generated by KiCad). It's almost finished.

    And here is a small section (of four IC's) :

    The TOP layer is RED, first inner layer is groundplane (not shown), second inner layer is ORANGE and the BOTTOM layer is BLUE. You can click on the picture for a better view.

    Yes, all routed by hand.

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Paul Driver wrote 08/31/2024 at 21:41 point

Dr Matt Regan on YouTube has an entire series on microcoded TTL computers, and has done 6205 emulation, culminating in an Apple II clone) as well as the Z80, culminating in both Sinclair ZX80+ and Spectrum clones.

https://youtube.com/@drmattregan?si=3HBWGR9niP8KzCvZ

  Are you sure? yes | no

Eric Hertz wrote 09/01/2024 at 02:03 point

Dr. Phil might have something to say about someone who has to spam every corner of another's creation...

The one in the "On The Cover of Hack A Day" log-entry really takes the cake.

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roelh wrote 09/01/2024 at 07:26 point

Hi Paul, in his video https://www.youtube.com/watch?v=y04AH5Q3Z3I  Dr Matt Regan shows his Z80 TTL system working. But he only implemented a (small?) part of the instruction set. It's not clear which instructions he implemented and which he left out. But his demo can only show the copyright message at the start of a ZX81. This could be done with less than 10 different opcodes. Isetta can handle more than 650 different opcodes for its Z80 mode.

His Sinclair Spectrum clone uses a regular Z80 cpu (https://www.youtube.com/watch?v=N36iWYcXBAE) and not a Z80 built from TTL.

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Con Cunningham wrote 04/21/2023 at 21:11 point

Just  been reading your square inch TTL CPU - great work. Did you publish your microcode, or is that proprietary ? Curious how you managed such a rich ISA with so few control signals!

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roelh wrote 04/22/2023 at 18:08 point

Hi Con, the microcode can be seen when you scroll down on the simulator page: 

http://www.enscope.nl/simas_nac/

Did you read the logs ? If you also look at the schematic,  ( https://hackaday.io/project/161251-1-square-inch-ttl-cpu/log/154913-schematic-of-the-cpu ) you should be able to understand how it works.

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Con Cunningham wrote 04/21/2023 at 20:51 point

I honestly don't know - perhaps when I get to wire-wrap some of it, and it starts to operate I might do so. Yes indeed, I use the 74181 as a 16 bit address incrementer, and of course, for all of the other 6502 arithmetic and logical ops.  Keep up the good work.

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Con Cunningham wrote 04/20/2023 at 21:03 point

An ambitious project. I know this because I have been working on something similar (When work allows) for some months. I am on my 3rd iteration. This time I have based my design roughly on Tanenbaum's "Structured Computer Organisation" , see https://csc-knu.github.io/sys-prog/books/Andrew%20S.%20Tanenbaum%20-%20Structured%20Computer%20Organization.pdf

I am using 74LS TTL, and have opted to make life easy by using 4 x 74181 as a 16 but ALU. I hope to implement all of the 6502 ISA, with the exception of Decimal Mode.

Have you begun to use a simulator, such as Logisim or Digital yet?

I wish you the very best of luck with your project, keep the updates coming!

Con

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roelh wrote 04/21/2023 at 20:03 point

Thanks Con !  I'm curious about your project. Will you publish it on Hackaday ? I suppose you will use the 4 x 74181 as address incrementer ? Yes I will soon start simulating.

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