Control section details

A project log for Isetta TTL computer

Retro computer built from TTL, with 6502 and Z80 instruction set. Includes video system.

roelhroelh 04/15/2023 at 21:150 Comments

In this log I talk about the 24 control signals that come from the microcode. The names of all signals that come from the microcode register will start with CTL.

The microcode will be organized in 3 bytes, the upper, middle, and lower control byte. The upper microcode has the longest description.


The first diagram shows the signals that select a condition and handles flags:

Flag update

Some instructions update flags, others don't. The signals CTL_UPD_C, CTL_UPD_Z and CTL_UPD_N indicate if the flags C, Z or N must be updated with a new value coming from the ALU_COUT, the ZERO detector at the output of the ALU, or bit 7 of the ALU output (R7, Result-bus bit7). If a flag is not updated, it will keep the same value.

There is no provision to read or write the flag bits as a full byte, like that is normally used in many 6502 designs. The microcode will have to read or write the flags one-by-one in order to push or pull the flags (or do EX AF,AF' for Z80).

Condition select

The signals CTL_C0, CTL_C1 and CTL_C2 select one of eight conditions. It is used for two different things:

Early condition evaluation

There is one more important thing to say about the condition selection. Suppose that we want tot test for a condition, and execute a conditional micro-instruction based on that, this would be 3 micro-instructions (3 cycles):

  1. Select the relevant condition, like C, Z or N, (putting this condition in FLAG_F)
  2. Fetch the next micro-instruction based on the FLAG_F value
  3. Execute the micro-instruction that was selected with FLAG_F

Number 1 and 3 are really needed, but in number 2 we are just waiting for the next micro-instruction coming out of the pipeline, and if we can not do something useful in that cycle, it is a 'lost cycle'. But we can do something about that. By connecting the signals CTL_C0, CTL_C1, CTL_C2 and CTL_WR_F not to the microcode register, but directly to the microcode ROM output, we can evaluate the condition one cycle earlier (at the end of the fetch phase). We now get the following two-cycle sequence:

  1. Select the condition. The selection has actually been done in the previous cycle, so in this cycle the new micro-instruction, based on the FLAG_F value, will be fetched.
  2. Execute the micro-instruction that was selected with FLAG_F

So we just gained one cycle for micro-instructions that use conditional execution.


The ALU control section must provide the control signals for the ALU. In the ALU log it is shown that the following control signals are needed:

So the ALU can be controlled with 11 signals. But we don't want to spend so many of the available micro-instruction bits for these. Fortunately, it is not difficult to bring this number of signals down to a reasonable amount.

Generating the DCBA control signals

The DCBA controls for the upper logic unit have bit A being '1' only in the case of a DEC instruction (and for complementing a value, but we don't use that). So bit A can be removed from the control wires and be regarded as a special case. 

The DCBA controls for the lower logic unit only use the patterns 0000, 1010 and 0101. Of these, the 0101 is only used in a single case (SUB, Subtract), so if we handle that as a special case we only need a single control signal CTL_ALU0 for choosing between 0000 and 1010.

To handle the special cases, we have a decoder (U5) that decodes the CTL_ALU1, CTL_ALU2 and CTL_ALU3 lines into 8 separate cases. The output of the decoder is activated (high) when the ALT/ signal is low. It handles the DEC and SUB cases and will also control the right-shift (CTL_SHR) as a special case.

Group 0 and group 1

The ALU operations are divided in two groups, selected by CTL_ALU3:

Group1 is the easiest to understand, this encompasses all arithmetic instructions (although also some logical instructions are in this group). The multiplexers at the right side of the drawing will do the following:

Group0 encompasses instructions where the adder is only used as pass-through, for some logic functions, for shift-right and for loading (moving) a value. This is also the group to use for writing a new value to FLAG_F. A single micro-instruction can write to FLAG_F and load a new value (at the same time). Multiplexer functions for group0 are:

Summary of upper control byte

The upper control byte has the five ALU controls in bits0-4 and the three condition selects in bits 5-7. The following diagram shows the ALU micro-instructions that are possible with the upper byte:


This will provide the following control bits (explained below):

Source and Destination

Most bits in this byte determine how the information flows in the CPU. A source and a destination are selected. The CTL_DST0, CTL_DST1 and CTL_DST2 determine the destination of a byte on the result bus:

The bit CTL_SRC determines the source for the databus. For destinations Memory and Output, the source is:

For destinations other than Memory or Output, the source is:


Almost all source and destination combinations need an address on the address bus. The address is determined by the CTL_M0 and CTL_M1 signals:

When the program counter is used to address memory, it will also increment. But if it's only used to access its value (like for storing a return address), it is not incremented.


This will provide the following control bits (explained below):

When the source is coming from the high or low address bus, it comes from the high address bus if CTL_HI is '1', and from the low address bus if CTL_HI is '0'.

In the register addressing mode,  the lower 3 bits specify 8 registers. If the CTL_HI bit is set, it specifies 8 other registers, but in this case there is an extra address bit that is provided by the Z80-exx flipflop. The result is that the upper 8 registers can be swapped for other registers by toggling this flipflop. It implements the alternative register set of the Z80.

Well, that's it. I hope I didn't forget a control bit.

The drawings in this log were made with Scheme-it.