• ### Breadboard adapter

01/04/2017 at 10:02 0 comments

I built a breadboard adapter on a perfboard yesterday. It has the logic probe and a clamp to a breadboard built by a small upside down section of perfboard with 11 x 4 holes. The clamp is fixed to the logic probe by 4 wires through both perfboards and soldering them on both sides. 4 pins hook to signal columns of the breadboard while 2 pins on each side connect to the power rail rows. I always use the convention of having ground on the inside rail and Vcc on the outside rail. The adapter can also be used to bridge power from one half of the power rail to the other.

A connector is provided at pin 9 of the ATTiny26 to plug in the probe. The DIP-switches are replaced with jumpers. The pictures show sound on, CMOS level. The LEDs are green for low, red for high and yellow for pulse.

• ### ADC Calculations

12/24/2016 at 11:42 0 comments

You may have noticed that the ADC is used in 8-bit mode as the ADLAR bit (ADC left adjust result) is set in ADMUX. At the same time we only use ADCH to determine the voltage thresholds. The reference voltage is set to Vcc. So we get 0 for ground and 255 for Vcc. Now we need to use the rule of three (also called the rule of proportion) to find the ADCH values for a certain percentage or voltage.

For CMOS the voltages are defined as <= 30% Vcc for low, >= 70% for high.

• ADCth = ADCHmax * Vth% / 100%
• ADClow = 255 * 30 / 100 = 76.5
• ADChigh = 255 * 70 / 100 = 178,5

Since we can only compare an integer with ADCH we need to cut off the result to an integer. The compare results are based on the carry flag of the compare. 0 = same or higher, 1 = lower. As we want to compare the lower threshold to be lower or equal we need to elevate the lower threshold by 1. I used ADClow = 77 and ADChigh = 178.

For TTL the voltages are defined as Vcc = 5V, Vlow = 0.8V and Vhigh = 2V

• ADCth = ADCHmax * Vth / Vcc
• ADClow = 255 * 0.8 / 5 = 40.8
• ADChigh = 255 * 2 / 5 = 102

Again we need to only use the integer part and elevate the lower threshold by 1: ADClow = 41 and ADChigh = 102

Why to cut off and not to round? Remember, the 2 least significant bits of the ADC result are also cut off, so an ADC result of 76.75 is still lower than 77. If we would have rounded 76.5 + 1 we would compare to 78 and that would actually be less accurate.

• ### 1k challenge

12/23/2016 at 11:37 0 comments

The size of the binary code from the bottom of the listing (Logic_Probe.lss):

```"ATtiny26" memory use summary [bytes]:
Segment   Begin    End      Code   Data   Used    Size   Use%
---------------------------------------------------------------
[.cseg] 0x000000 0x0000dc    220      0    220    2048  10.7%
[.dseg] 0x000060 0x000060      0      0      0     128   0.0%
[.eseg] 0x000000 0x000000      0      0      0     128   0.0%
```
I used Atmel Studio 6.1 to assemble the source code.
• ### TTL open level

12/22/2016 at 13:21 0 comments

just noticed that the input thresholds for TTL are not compatible with the resitor network on the probe pin. >= 2.0V is TTL high but the resistors source ~ 2.5V compatible with CMOS thresholds. One more resistor and an output pin of the ATTINY should do the trick.

update: The Problem was fixed by a redesign of the probe precharge resistor network and bypassing the resistor connected to Vcc in CMOS mode.