The simplest 4-bit RISC CPU

In this project, I attempt to build a very simple 4 bit RISC CPU.
The goal was to design a RISC processor and computer.
*Sponsored by PCBway

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The goal was to design something like a RISC processor and computer, using the smallest amount of TTL chips and parts.
It is not intended for practical applications. (I would rather use Arduino or Raspberry Pi for practical system.)

* This project is sponsored by PCBway, full feature custom PCB prototype service.

There are many prior examples of 4-bit CPU projects.

For example, a 4-bit CPU (TD4 once again) by Fedor Gruzdev

I want to design something even simpler and elegant using minimum parts. The purpose is to build something educational, that we can call

"a computer" to learn the concept and basic parts of RISC CPU and a computer operation, without breaking a budget and unnecessary complications.

The architecture must be simple but extendable. All parts must fit on a single PCB. The state, registers and operations of the CPU must be displayed by LEDs.

Here are the design choices:

* The CPU uses only TTL chips.

* Processor uses Harvard architecture with program memory in a single EEPROM.

* Minimum number of instructions for Turing complete machine.

* There is no RAM memory, but it can be added in later designs.

The resulting 4-bit RISC CPU schematics is shown here.

It is probably the simplest 4-bit CPU one can construct from TTL logic chips!

It consists of only 7 TTL chips, one EEPROM program memory, and 555 timer for generating a clock signal.

All instructions execute in 1 cycle. This simplifies cpu control logic.

The processor uses 2 phases clock: On positive edge of the clock (0 to 1), ALU executes instructions clear and Add.

On negative edge of the clock (1 to 0), instruction address counter increments, or loads next instruction address (i.e does Jump instruction).

The clock frequency is intentionally low, from 1Hz to 1000 Hz.

Possible manual button operation for step by step debugging, if using additional switch instead of the clock.

Outputs of all registers and memory are displayed by LEDs.

The CPU is 4-bit. With 4-bit data and address buses. The 8-bit instruction consists of 4-bit address/immediate data, and 4-bit instruction opcode.

ALU and only one register A (Accumulator) are 4-bit wide.

Instruction address counter is 4-bit wide, that means the address space is up to 16 instructions. Although the EEPROM chip has much more space.


Principle of operation:

the 555 timer generates clock signal CLK, adjustable from about 1 Hz to 1000 Hz.

The output is inverted to make the opposite phase of the clock or inv. CLK.

The ‘reset’ button makes ‘clear’ signal for the instruction counter and registers.

The 74SL161 is a 4-bit instruction address counter. The address counter is incremented on the edge of inverted clock (inv. CLK). It is reset to 0 when reset button is pressed.

When ‘inv. Load Addr’ signal it low, the address counter loads next address from the address/data bus, i.e. it executes Jump instruction.

The instruction address goes to the address inputs of the EEPROM.

There are two flip-flop registers 74LS173. One is 4-bit A register (accumulator), another is Flag register. Registers store data on the positive edge of CLK clock. *

(Obsolete flip-flop 74LS173 is replaced with 74LS175.)

The 74LS283 adder is a 4-bit ALU. It adds values from data bus and from A register (accumulator) and stores result to the accumulator. The carry output signal is stored in the Flag register.

All register values and instruction/data are displayed by LEDs.


There is one CPU flag ‘carry’, which is saved after the last Add instruction.

The instruction is 8-bit wide (output of the program EEPROM).

Low 4 bits of instruction is immediate data or address. High 4 bits is the instruction opcode.

It is possible to implement “up to” 16 instructions.

But the CPU has only 5 instructions, here with opcodes (hex):

0 - Noop

1 - Clear register A (accumulator) and Flag register.

2 - Add immediate to A and save to A.

4 - Jump conditional (when flag Carry is 1)

8 - Jump (unconditional)

Notes: the instruction set is small to simplify the control logic. One bit signify the instruction....

Read more »


4-bit RISC CPU, fully assembled.

JPEG Image - 74.32 kB - 08/03/2023 at 06:06



PCB just manufactured by PCBway

JPEG Image - 219.97 kB - 07/06/2023 at 02:52



PCB RISC CPU v1.2 2nd PCB revision

Adobe Portable Document Format - 207.39 kB - 06/18/2023 at 17:17



Schematics RISC CPU v.1.2 with 75LS175 flip-flops

Adobe Portable Document Format - 146.62 kB - 06/18/2023 at 17:15


Adobe Portable Document Format - 136.42 kB - 05/27/2023 at 20:18


  • Spare PCB for sale

    Marsianin24509/12/2023 at 20:23 0 comments

    I have a few spare PCBs for sale for 4-bit RISC CPU.
    I can sale them. If interested, send me email or private message 
    to Marsianin245.

  • CPU fully assembled

    Marsianin24508/03/2023 at 06:05 0 comments

    Fully assembled 4-bit CPU and tested simple program on it.
    For example this program code executes in a loop:
    address   code (hex)    instruction
    0              00        No-op
    1                10        clear A
    2               21        Add 1
    3               21        Add 1
    4               22       Add 2
    5               81        Jump on 1

  • partially assembled PCB

    Marsianin24507/25/2023 at 05:13 0 comments

    partially assembled and tested: 5v vcc supply, timer, instruction counter.
    Timer is generating clock approximately 1 Hz.
    Instruction counter increments on falling edge of clock pulses,
    counts from 0 to 15.

  • fixed 74LS01 mistake

    Marsianin24507/22/2023 at 04:01 0 comments

    Found small mistake in the schematics. Inadvertently used chip 74LS01 with open collector. Should have used Simple NAND gate 74LS00. To fix this one simple way is to replace it with 75LS00. But PCB is already done. And pinout of 74LS00 chip is different. So the simplest other fix - is to put small pullup resistors about 1 k,  between outputs of 74LS01  pins 13 and 10 and +5 v to pull pins up.

  • PCB manufactured

    Marsianin24507/06/2023 at 02:51 0 comments

    Just received PCB from PCBway. See photo 1. Ordering from PCBway was very easy, in just a few clicks.
    1. Select PCB size and type, 2. Upload the Gerber file. 3. Select address and delivery.

    The PCB was manufactured quickly and delivered in less than one week.
    Quality of 2-layer PCB looks good to the eye inspection.
    Next step - is to assemble the RISC cpu.


  • Schematics v1.2 and PCB

    Marsianin24506/18/2023 at 17:20 0 comments

    Schematics v1.2 and PCB 2nd revision

  • 4-bit cpu schematics 1.2

    Marsianin24506/14/2023 at 01:39 0 comments

    I realized that the flip-flop chip 74LS173 is obsolete and no longer available.
    Replaced the obsolete 74LS173 with other TTL flip-flop 74LS175.
    Added jumper and switch for manual step clock operation,
    Added 5v voltage regulator and bypass capacitors.
    The new schematics revision 1.2 

  • Logic simulation

    Marsianin24506/04/2023 at 20:28 0 comments

    Simulated the 4-bit CPU logic in Logicsim simulator to verify the design. Logical model includes all chips, registers and EEPROM memory.
    Simulated execution of short programs by the processor. For example, simulated this program

    instruction (byte); upper 4 bits: opcode; lower 4 bits data/address

    00  -  no-op:   nothing happens

    10   -  clears A register;   A: 0

    21   - Add 1 to A;               A: 1

    24  - Add 4 to A;              A: 5

    25  - Add 5 to A;              A: 10

    21   - Add 1 to A;               A: 11

    40  - Jump conditional to address 0, if flag carry is on;  false

    26  - Add 6 to A:              A: 1 and Flag carry 

    41   - Jump conditional to address 1, if lag carry is is on; true   Jump executed on address 1

View all 8 project logs

  • 1

    Assembly components on the PCB per schematics.

    All TTL chips and components can be soldered directly on PCB.

    *Recommended to install EEPROM chip U3 on a DIP 24 pin socket, so that EEPROM could be easily removed and reprogrammed when needed.

    *Note: U10 chip HD74LS01P has open collector output.
    If using TTL chip HD74LS01P as U10, per diagram, add pull up resistors 1k to output pins 10 and 13 of the chip to the VCC.
    Or use chip HD74LS00P instead. But that requires change the PCB because this chip has different pin out diagram.

    *Resistors 330 for LED current limiting can be replaced with 1k resistors. But LED brightness may be reduced.

  • 2
    4-bit RISC CPU Programming instructions

    CPU has only 5 instructions, here with opcodes (hex):

    0 - Noop

    1 - Clear register A (accumulator) and Flag register.

    2 - Add immediate to A and save to A.

    4 - Jump conditional (when flag Carry is 1)

    8 - Jump (unconditional)
    Instructions are stored in EEPROM from address 0.

    The upper 4 bits of instruction is the opcode. The lower 4 bits are immediate add operand or address of Jump instruction.

    Address space of instructions is 4 bits from 0 to 15. Program execution starts from address 0, after pressing reset button. Each instruction executes in one cycle. Jumper on PCB is used to select clock signal source, from 555 chip or from the manual clock button.

    Instruction set is designed such that each bit of opcode encodes one instruction to simplify decoding logic.

    There is no Subtract instruction. But one can subtract by adding a ‘binary complement’ of the number in immediate value. For example subtracting 1 is equivalent to Add binary compliment  (hex value F) to A.

    There is no load A instruction. To load value to register A, use ‘Clear’ instruction opcode 1, following by ‘Add’ instruction opcode 2 to load value to the A accumulator. 

  • 3
    Step 3

    Example of simple program for this CPU:

    Clear A accumulator, then continue add 1 to Accumulator register, until the value exceeds 15. 
    Uses Add, Jump, and Jump when overflow instructions.
    Program EEPROM contents
    Address   instruction code (hex)   comment

    0              00                                   no op

    1                10                                    clear accumulator

    2               21                                    add 1 to accumulator

    3               41                                    Jump to address 1, if overflow flag

    4               82                                   Jump to address 2.

View all 3 instructions

Enjoy this project?



Elbert wrote 08/04/2023 at 07:47 point

Would an one-instruction set CPU ( even give less electronics?

  Are you sure? yes | no

Marsianin245 wrote 08/06/2023 at 02:08 point

May be 1 instruction would be simpler. But it was not the objective of this design. Objective was to make simple processor that still resembles the 'real' risc cpu architecture. And can do some 'real' arithmetic operations and do jump and conditions.

  Are you sure? yes | no

Marsianin245 wrote 06/15/2023 at 01:30 point

I think you can test the condition that accumulator is nonzero. if jump is not happened then A is zero.
2F    add F to accumulator. if nonzero carry flag will set
4n    if carry flag is 1, jump to address n
8m    jump to address m  
address n
address m          


  Are you sure? yes | no

Alvaro Barcellos wrote 06/14/2023 at 18:04 point

How implement the "jump when acumulator is zero" ?

  Are you sure? yes | no

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