* This project is sponsored by PCBway, full feature custom PCB prototype service.
There are many prior examples of 4-bit CPU projects.
For example, a 4-bit CPU (TD4 once again) by Fedor Gruzdev
I want to design something even simpler and elegant using minimum parts. The purpose is to build something educational, that we can call
"a computer" to learn the concept and basic parts of RISC CPU and a computer operation, without breaking a budget and unnecessary complications.
The architecture must be simple but extendable. All parts must fit on a single PCB. The state, registers and operations of the CPU must be displayed by LEDs.
Here are the design choices:
* The CPU uses only TTL chips.
* Processor uses Harvard architecture with program memory in a single EEPROM.
* Minimum number of instructions for Turing complete machine.
* There is no RAM memory, but it can be added in later designs.
The resulting 4-bit RISC CPU schematics is shown here.
It is probably the simplest 4-bit CPU one can construct from TTL logic chips!
It consists of only 7 TTL chips, one EEPROM program memory, and 555 timer for generating a clock signal.
All instructions execute in 1 cycle. This simplifies cpu control logic.
The processor uses 2 phases clock: On positive edge of the clock (0 to 1), ALU executes instructions clear and Add.
On negative edge of the clock (1 to 0), instruction address counter increments, or loads next instruction address (i.e does Jump instruction).
The clock frequency is intentionally low, from 1Hz to 1000 Hz.
Possible manual button operation for step by step debugging, if using additional switch instead of the clock.
Outputs of all registers and memory are displayed by LEDs.
The CPU is 4-bit. With 4-bit data and address buses. The 8-bit instruction consists of 4-bit address/immediate data, and 4-bit instruction opcode.
ALU and only one register A (Accumulator) are 4-bit wide.
Instruction address counter is 4-bit wide, that means the address space is up to 16 instructions. Although the EEPROM chip has much more space.
Principle of operation:
the 555 timer generates clock signal CLK, adjustable from about 1 Hz to 1000 Hz.
The output is inverted to make the opposite phase of the clock or inv. CLK.
The ‘reset’ button makes ‘clear’ signal for the instruction counter and registers.
The 74SL161 is a 4-bit instruction address counter. The address counter is incremented on the edge of inverted clock (inv. CLK). It is reset to 0 when reset button is pressed.
When ‘inv. Load Addr’ signal it low, the address counter loads next address from the address/data bus, i.e. it executes Jump instruction.
The instruction address goes to the address inputs of the EEPROM.
There are two
flip-flop registers 74LS173. One is 4-bit A register (accumulator),
another is Flag register. Registers store data on the positive edge
of CLK clock. *
(Obsolete flip-flop 74LS173 is replaced with 74LS175.)
The 74LS283 adder is a 4-bit ALU. It adds values from data bus and from A register (accumulator) and stores result to the accumulator. The carry output signal is stored in the Flag register.
All register values and instruction/data are displayed by LEDs.
There is one CPU flag ‘carry’, which is saved after the last Add instruction.
The instruction is 8-bit wide (output of the program EEPROM).
Low 4 bits of instruction is immediate data or address. High 4 bits is the instruction opcode.
It is possible to implement “up to” 16 instructions.
But the CPU has only 5 instructions, here with opcodes (hex):
0 - Noop
1 - Clear register A (accumulator) and Flag register.
2 - Add immediate to A and save to A.
4 - Jump conditional (when flag Carry is 1)
8 - Jump (unconditional)
Notes: the instruction set is small to simplify the control logic. One bit signify the instruction....Read more »