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First Load Stage Testing

A project log for 10kW (30kW pulse) Electronic Load

All we need to do get some big resistors and connect them up in different combinations, right?

tinfevertinfever 06/27/2023 at 03:200 Comments

It's alive! Testing of the first load stage has begun. I'm starting with the 8R load stage to start small, and then I'll work my way up.

Here is the current schematic of the load stage, in case anyone is curious. The same PCB is designed to support load resistors from 8R to 0.1R (thus currents from 1.5A - 122A) with different component configurations. KiCad doesn't have a good system for handling variants so you can't tell from the schematic which components I've loaded for this 8R load stage. I have the variant details in various part fields which does sort-of integrate with the interactive BOM generator though. The important variant details are: only one FET is populated as a SIRA18ADP, only one SS1H10 flyback diode, the "boost" section isn't loaded, and a single 16 mOhm current shunt.

Overall, it's working well with the exception of two issues.

  1. When I started ramping up the voltage across the load, above about 10.5V, it would start to oscillate at a frequency of around 72 MHz on the turn-off transition. It was bad enough that it wasn't actually turning off at all. I don't fully understand it, but I believe this was due to a capacitor I added between the MOSFET gate and drain in order to slow the turn-off fall-time to reduce the inductive overshoot. I think during turn-off as the voltage across the FET started to rise, current was flowing through that cap causing the gate to rise as well, which turned the FET on so the voltage across it falls, until the gate driver has discharge the gate enough that the FET starts turning off again and the cycle repeats. I believe this is called dV/dT turn on, and I've exacerbated it by adding that cap (C25). Removing the cap fixed the issue, and the inductive spike overshoot is quite manageable right now (14.6V on a 12.2V supply). I'm curious if there is a way to fix it without removing that cap though.
  2. There is a 30us delay between the FET_EN signal going low, and the FET gate actually going low. I need to look in to this more. I'm suspecting the optocoupler might be causing this. I know optocouplers can be slow but I didn't think they would be that slow. In theory, I could compensate for the turn-off delay in software, but I have a hunch it won't be consistent over all load input voltages since the load input is actually used to power the gate drivers and opto pull-up.

Remaining to be tested:

Bottom signal is FET_EN, middle signal is gate voltage, top signal is I_SENSE output. Running at 3kHz no problem, except for turn-off delay.
Turn-on time is reasonable and expected at around 2us. The current rises faster than shown here because the current sense amp is limited to 150kHz bandwidth.

Turn-off delay shown here between FET_EN and gate voltage is quite bad at roughly 35us.

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