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• A very very very small milestone

  Forthnutter • 05/16/2026 at 04:15 • 0 comments

  I made very small milestone in my quest. I have created the equation In WinCUPL with inputs 30Mhz and 15Mhz and generated 7.5Mhz, 3.75Mhz and 1.825Mhz. Put JED file into spare GAL16V8 with GALEP-4 (amazing that thing still works). And bang it works Yes!.

  Now on to the next stage put all the other signals in on this Timing PAL.

• Minor Update

  Forthnutter • 05/15/2026 at 14:11 • 2 comments

  In the previous picture, I have made some errors on the analyser labels. I have removed the reset signal, i have run out of analyser inputs. I tied it to VCC not needed at this stage. I have been focusing on clock signal.

  An interesting thing is the 1.825Mhz is out of phase with 3.75Mhz clock. All other clocks seems to clock on the rising edge.

  I am will try and see if I can make the equation and simulate that with WinCUPL.

• The Logic Analyser

  Forthnutter • 05/12/2026 at 00:32 • 0 comments

  I used the Analog Discovery 2 to Power the PAL and send signal to inputs and read the output of the PAL.

• The Decoding of the U51 TPAL2

  Forthnutter • 05/11/2026 at 14:26 • 1 comment

  I start to decode the U51 TPAL2 PAL16R8 today.  Made an interesting discovery, I notice that the RAM CASL and CASU signals are swapped. Scratching my head, thinking why ?.

  This must have been a slight design error and the designer decided to correct the error within the PAL. So the UDS signal turns into CASL and LDS  is CASU.

  Here is a quick snap shot of signal don't panic the timing is not correct, I stimulated the clock signals with the logic analysers wave generator. More to come.

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