I think I've tweaked the component values into something possibly usable. The feedback resistor seems to improve the speed tremendously - by keeping the transistors out of saturation - at the cost of greatly reduced gain. But maybe we don't need that much gain? Here are the latest component values:
the feedback resistor is new. It keeps the voltage on either base away from the rails to prevent either transistor saturating. An unfortunate side effect of this arrangement is a greatly reduced gain - at DC, the gain is approximately the ratio of the two resistors 2.2k / 1.6k = 1.375. Yes, this is very small - I thought it would be too small to be useful, but maybe it's OK, if you're careful. To get a feel for just how small this is, here's the voltage transfer function, which would normally be a sharp step function for an inverter:
For most of the input voltage range, this is a linear amplifier. It's only at the extremes that it starts to look like a logic gate. But, since the output stage is symmetrical and low-impedance, and the input stage high-impedance, maybe this is enough gain to build logic circuits. Theoretically, you only need a gain of 1 after any losses...
Then again, consider the speedup capacitor. At 10 MHz, that 100 pF capacitor has an impedance of about 160 ohms, so the gain is now around 14. That doesn't sound so bad.
I built an early hardware test (with different RC values) of a ring of inverters with feedback resistors. At 1.1V supply, they were happy to just sit there and bias themselves to 1/2 the supply without oscillating - the gain was too low. At 1.2V, they always started ringing, and once started, they kept going as the supply was turned down to about 0.7V. So, I started simulating things at 1.2V instead of 1.1. The final supply voltage will probably need a tuning knob.
The original problem from a few logs back was that the logic worked well with high-speed square waves, but not at low or high duty cycles. I'm convinced now that rapid switching was keeping the pair out of saturation. A short pulse after a sustained high or low input wasn't enough to pull one of the pair out of saturation. The added feedback resistor holds the base voltage close to the midpoint, keeping both transistors out of saturation. This allows the gate to respond to brief, isolated pulses as well as waveforms with high repetition rates. Here's a test waveform at the input and output of a chain of 10 inverters:
The measured delay for 10 inverters is around 16 ns, or 1.6 ns per inverter. This is significantly faster than what I had seen before. I haven't constructed any of these inverters yet, so I can't be sure it will work with real components. The initial low period above is a test for the saturation problem. Without the feedback resistor the PNP saturates on the initial stretch, and we get this - no output at all:
I suspect the output would eventually start switching because this is only a 5 MHz square wave, but I didn't let the simulation run that long.
In this simulation, the second-to-last stage drives a fan-out of 10 inverters.
This slows down the trailing edge of the first pulse so that it happens at a 31 ns delay (instead of 16 ns with the simple inverter chain). With a fan-out of 5, the delay is 24 (as opposed to 16) - so maybe a rough rule of thumb is that fan-out is roughly equivalent to cascading stages. It looks like driving 2 inputs delays the signal about as much as chaining 2 inverters. If the delays were all due to RC effects, this would be the case. This is not great, but might be acceptable. Again, I haven't measured this on the hardware yet.
In any case, increasing fan-out decreases switching speeds. You see this with CMOS logic where the input capacitance of added driven inputs slows down the transition speeds. Although with integrated CMOS families, the effect is not this pronounced.
I roughly estimated the output impedance of the stage at 9 ohms. The input impedance is above 1.6k until about 350 kHz, then drops to about 200 ohms at 10 MHz. The vertical axis is labeled in volts because I used an AC current source to probe the input impedance.
I won't paste plots here, but these gates drive 50 or 100-ohm terminated lines just fine. I tested outputs with split-terminations of 100 ohms to ground and V+ (for 50 ohm lines) and 200 ohms to each (for 100 ohm lines). No problems at all, which is what you'd expect from under 10 ohms output impedance. With fast edge rates, you might have to use terminated lines to maintain signal integrity. Of course, you can also source-terminate transmission lines, but you can't fan-out and source terminate (unless your transmission lines are exactly the same length). I didn't look at how many split-terminated loads you can drive - but at least (2) 100-ohm loads, since you can drive (1) 50-ohm load.
These component values translate straightforwardly into the NAND design:
In simulation, the upper input shows a delay of about 2.3 ns, and the lower input shows about 3.6 ns. It may be possible to balance these somewhat by tweaking the component values a little, but I haven't had a chance to try yet. Like the inverter, the NAND has no problem with saturating during long periods of stationary input values; the feedback resistor has cured the mysterious square-wave illness.
I need to build some of these gates from actual components and see if they perform as well as the virtual ones. The low DC gain of these stages troubles me a little, but I think the logic is still workable.
UPDATE 20170121 : How much gain is actually required?
I was a little hesitant at first about the low gain of these gates. Then I started thinking about the minimum gain that would be required to meet commercial CMOS family specs. Here's what a worst-case (lowest gain) transfer curve would look like that still meets the Vih, Vil, Voh, and Vol specs from a datasheet:
For the 74HC04 at 6V supply and with all worst-case values, we get (5.2 - .4)/(4.2-1.8) = 2.0. At a 2V supply, it's (1.9-0.1)/(1.5-0.5) = 1.8. Hmm, maybe 1.375 isn't that crazy after all.