In the first log entry I showed a checkerboard image on the screen where the last line looked like it was out of sync. I just realized that the syncs are just fine (even if the screen is not rock stable - but what can be expected with an internal mcu oscillator PLL'ed up by 4?).

It's actually the top line (no 1 of 7) of the first pixel row that is shown as the last line. The lines are all offsetted by one.

I realized that I use the idle time in the sync pulse interval in the subroutine that outputs the lines with with video data to increment the 1-of-7 counter and update the pixel counter. This is done *before* the video is output, meaning that the I've skipped the very first row and it will turn up as the last line after a premature wrapping of the counters.

Easy fix. Initially at boot initialize the 1-of-7 counter with 0xFF instead of 0x00 - then it will all line up nicely :-)

Actually I'm using a down-counter decrementing from 7 to 0 with a "decfsz" instruction, so the initial initialization value should be incremented by one to get it all adjusted correctly.