Let's talk about RiscV.

In the 80s and 90s its design principles and implementations would have been absolutely wonderful. But we're in 2025 and the RISC-V architecture is ... a big disappointment on many levels. I won't go into details why but the simple fact that I design YGREC32 will prove some of my points.

The problem is : nobody expects YGREC32 or F-CPU, everybody "wants RISC-V", yet is unable to say why, apart from "that's what everybody else wants". And they don't want to pay an ARM or a LEG for a license. And there are tons of "free cores that implement it already". Just don't look at the details, or the favourable comparisons with x86 start to vanish.

Now what can I do ?

My Grogu is determined to design a RISC-V SoC and there is no way to stop him, the Force is so strong with him, but I fear he will corner himself sooner or later, trying to oblige to "market pressure" and despite my attempts, I'm unable to help him on that outdated architecture. Damnit, I'm too old and cranky to even feel comfortable using a 6809 or even 6309...

But the "baseline" RV arch is designed on extensibility, leaving the 2 LSB cleared for "later use", and the base opcodes have MSB=00. Meanwhile, Y32 has 3 pipelines, each could have one of of the remaining MSB combinations:

• 00 : RV
• 01 : Y32-control/stack
• 10 : Y32 data pipeline / glob0
• 11 : Y32 glob1

So with some work, it would be possible to "graft" Y32 over a RV32 core, maybe as an "accelerator" or something, or a "bi-mode" processor, and later jettison RV32, or even worse : reintegrate certain Y32 features back into the RV32 core. I can hear Dave Patterson howl at the moon from here.