This double Eurocard processor offers unique flexibility for real-time systems designers: a high-performance 68020 VMEbus CPU with hardware suited to cost-effective implementation of embedded systems, coupled with an additional interface to STEbus on the outer rows of P2. This secondary bus provides the option of utilising the low-cost single Eurocard STEbus board system.

On-board features include a 68020 CPU with cache running at 16-, 20- or 25-MHz, a socket for the 68881 maths co-processor, up to 2 Mbytes of zero wait-state dynamic RAM dual-ported to the VMEbus, 32 Kbytes of battery-backed static RAM dual-ported to the STEbus, two serial ports with access via either the front panel or an on- board 10-way header connector, two EPROM sockets jumper-selectable for up to 256 Kbyte devices, watchdog timer and battery-backed real-time clock.

The VMEbus interface supports 8, 16 and 32-bit data transfers with an addressing capability up to 4Gbytes, and includes a single-level arbiter, source for system clock and reset. Interrupts can be link-selected and prioritised from the real-time clock, serial ports, watchdog timer, VME and STE buses, BERR time-out and AC FAIL.

Four LEDs on the front panel provide indication of SYSFAIL and RUN/HALT status, and two user programmable diagnostics. VSC020T is designed for a high degree of inter-compatibility with Arcom's STEbus 68020 processor, SC020T. For many applications this allows target system hardware to be very easily upsized/downsized as the full application requirements emerge during the design cycle, eliminating one of the commonest and most costly problems of real-time systems design.

Comprehensive software support includes the multi-tasking ROMable operating system OS-9/68K, and a complete range of I/O board drivers.

VMEbus Interface

A32/24/16, D32/16/8 (E0) AM 09, 0A, 0D, 0E, 29, 2D, 39, 3A, 3D, 3E as master. A24, D16, D8 (E0) as slave.

STEbus Interface

Master and slave

Power consumption

Typ 4.8A @ 5V, 50mA @ +12V

Ordering Information

VSC020T-16    16MHz CPU, 1Mb DRAM
VSC020T-20    20MHz CPU, 1Mb DRAM
VSC020T-25    25MHz CPU, 1Mb DRAM
VSC020T-162   16MHz CPU, 2Mb DRAM
VSC020T-202   20MHz CPU, 2Mb DRAM
VSC020T-252   25MHz CPU, 2Mb DRAM

Features:

• 16, 20 or 25MHz 68020 CPU with 64 long word cache
• 1 or 2Mb zero wait-state DRAM; 32-bit organised,
  1Mb dual-ported to VMEbus, top 32Kb used as inter-bus mailbox
• Two EPROM sockets (16-bit organised) for up to
  512Kb EPROM
  32Kb battery-backed static RAM dual-ported to STEbus
• 68881 co-processor socket
• Watchdog timer
• Battery-backed real-time clock
• Comprehensive interrupt scheme
• VMEbus interface
• STEbus interface