In my previous log I shared the code I used to configure the Si5351 to generate two 100 MHz clock signals that were 90 degrees out of phase. However, looking at the outputs on the scope more closely, I now see that they were actually more like 70 degrees out of phase. You can see this in the capture I shared previously.
After a bit of trial and error, I've discovered that I can fix this by setting the multi-synth stages to fractional (rather than integer) division mode. i.e. Set bit 6 of registers 16 and 18 to zero. (I'm using the clk0 and clk2 outputs.) With the Si5351 library I'm using, this can most easily be done by setting up the dividers using configure_fractional
rather than configure_integer
.
Here's the updated code:
import board import busio import adafruit_si5351 # Set the following environment variable when using the Pico: # export BLINKA_U2IF=1 i2c = busio.I2C(board.SCL, board.SDA) si5351 = adafruit_si5351.SI5351(i2c) # 25 MHz (crystal) * 24 = 600 MHz si5351.pll_a.configure_integer(24) # 600 MHz / 6 = 100 MHz si5351.clock_0.configure_fractional(si5351.pll_a, 6, 0, 1) si5351.clock_2.configure_fractional(si5351.pll_a, 6, 0, 1) # 90 degree phase offset for output 0 si5351._write_u8(165, 6) si5351.reset_plls() si5351.outputs_enabled = True
And here's what the outputs now look like on the scope (AC coupled as before):
The phase shift still isn't exactly 90 degrees as measured by the scope, but this is visibly better than what I had before. I'll call this is good enough for now...
One final thought... The fact that the divider needs to be set to an integer value in order to obtain a shift of exactly 90 degrees is well documented on the web. However, I've not seen anyone mention that fractional division mode must also be used. This is curious, since using integer division mode is said to reduce jitter, so it's likely plenty of people have tried to generate a 90 degree phase shift while using it. Given this, I'm surprised I've not seen this documented, which makes me wonder whether I'm missing something?
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